category: Test, Measurement and Analytics

category: Auto, Security & Edge AI

One Test Is Not Always Enough
By Anne Meixner - 12 Oct, 2021 - Comments: 0

To improve yield, quality, and cost, two separate test parameters can be combined to determine if a part passes or fails. The results gleaned from that approach are more accurate, allowing test and quality engineers to fail parts sooner, detect more test escapes, and ultimately to improve yield and reduce manufacturing costs. New data analytic platforms, combined with better utilization of s... » read more

Don’t Let X Be A Problem For Logic BIST
By Rahul Singhal - 12 Oct, 2021 - Comments: 0

By Rahul Singhal and Giri Podichetty A failure in the operation of integrated circuits (ICs) or chips deployed in safety-critical applications such as automotive, medical, and aerospace could have catastrophic consequences. These failures could stem from defects in the chip that escaped manufacturing tests or from transient faults that can occur during system operation due to factors such as... » read more

PCB And IC Technologies Meet In The Middle
By Bryon Moyer - 12 Oct, 2021 - Comments: 1

Surface-mount technology (SMT) is evolving far beyond its roots as a way of assembling packaged chips onto printed circuit boards without through-holes. It is now moving inside packages that will themselves be mounted on PCBs. But SMT for advanced packages isn’t the same as the SMT we’ve been used to. “Many systems include multiple ASICs, a lot of memory, and that's all integrated i... » read more

Packetized Test At The International Test Conference 2021
By Geir Eide - 12 Oct, 2021 - Comments: 0

At this year’s International Test Conference (October 10-15, 2021), Siemens Digital Industries Software is showcasing IC test and lifecycle management technologies that address the key scaling challenges facing the semiconductor industry now and in the future. The two main topics from Tessent at ITC are: The rapid adoption of packetized test strategies to address design and system... » read more

Advanced Outlier Die Control Technology In Fan-Out Panel Level Packaging Using Feedforward Lithography
By Onto Innovation - 12 Oct, 2021 - Comments: 0

The growing demand for heterogeneous integration is driven by the 5G market that includes smartphones, data centers, servers, HPC, AI and IoT applications. Next-generation packaging technologies require tighter overlay to accommodate a larger package size with finer pitch chip interconnects on large format flexible panels. Fan-out panel level packaging (FOPLP) is one of the technologies that... » read more

High-Speed Image Processing By GPU
By Advantest - 12 Oct, 2021 - Comments: 0

By using CPU and GPU together, we have increased the speed of the filter function that is often used in imaging tests. This feature is provided by the Image Processing Library (IPL) in T2000 CMOS Image Sensor Solution. Next IPE, our new image processing engine that is currently in development, is about six times faster than IPE3 (Image Processing Engine 3), an existing engine. Author: Chiezo... » read more

Accelerating Verification Shift Left With Intelligent Coverage Optimization
By Synopsys - 12 Oct, 2021 - Comments: 0

Functional verification dominates semiconductor development, consuming the largest percentage of project time and resources. Team members look at the rate of design bug discovery, consider anecdotal information on the types of bugs that escaped to silicon in previous projects, and use their best judgment based on their years of experience to determine when to tape out. Above all, they look at v... » read more

Growing Challenges With Wafer Bump Inspection
By Ed Sperling - 11 Oct, 2021 - Comments: 1

As advanced packaging goes mainstream, ensuring that wafer bumps are consistent has emerged as a critical concern for foundries and OSATs. John Hoffman, computer vision engineering manager at CyberOptics, talks about the shift toward middle-of-line and how that is affecting inspection and metrology, why there is so much concern over co-planarity and alignment, how variation can add up and creat... » read more

Optimizing AI Systems
By Ed Sperling - 29 Sep, 2021 - Comments: 0

Inserting AI and machine learning into chips adds a whole new dimension of complexity, and creates a variety of potential problems, including deadlocks, loss of performance, and difficulty in achieving closure on many fronts. Gajinder Panesar, fellow at Siemens EDA, talks with Semiconductor Engineering about what’s changed and how to optimize these new devices and systems by monitoring them f... » read more

SLM Is Changing The Complete Device Lifecycle Process
By Ramsay Allen - 13 Sep, 2021 - Comments: 0

Amit Sanghani, Vice President of Engineering, HW-Analytics and Test Group at Synopsys, discusses how Silicon Lifecycle Management (SLM) is changing the way we look at the complete device lifecycle process and how it can enable heightened levels of visibility in device performance, reliability and security. Learn how SLM is well placed to address the challenges that occur at every stage of cut... » read more

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