$60B fab buildout; Chinese automakers tout 100% homemade chips; 2nm custom SRAM; Cadence’s virtual platform buy; multi-chiplet NoC; HBM roadmap; MIT’s GaN fab technique; 30% tax credit; Taiwan export restrictions, power vulnerability; global memory market; rad-tolerant memory; 2D, non-silicon computer.
Texas Instruments will invest more than $60 billion to build and expand seven semiconductor fabs in Texas and Utah, supporting more than 60,000 U.S. jobs.
Chinese automakers — including SAIC Motor, Changan, Great Wall Motor, BYD, Li Auto and Geely — are aiming to launch new models with 100% homemade chips, some as early as 2026, reports Nikkei Asia.
Marvell introduced 2nm custom SRAM tailored for AI and cloud data center applications, with up to 6 Gb of high-speed memory, 3.75 GHz operating frequency, and a 66% reduction in standby power compared to standard SRAM.
Cadence acquired VLAB Works, maker of ultra-high-performance virtual platforms, which Cadence plans to integrate into its verification flow. VLAB Works is a division of Australian Semiconductor Technology Corp. Terms of the deal were not disclosed.
Arteris expanded its multi-die network on chip (NoC) IP, adding cache-coherent read/write across multiple chiplets, which makes multi-die systems look like a single device, as well as optimized connectivity and registers, and standards-based support for die-to-die controllers and PHYs.
A number of EDA companies, including Siemens, Cadence and Synopsys, announced product certifications on Samsung Foundry’s advanced process nodes and other joint development agreements.
MIT researchers introduced a fabrication technique that selectively bonds tiny GaN transistors onto standard silicon CMOS chips using low-temperature copper bonding. This approach enables high-speed performance with minimal cost and heat, and maintains compatibility with existing foundry processes.
KAIST’s TERALAB published a 371-page deep-dive HBM roadmap, detailing enhancements through HBM8.
Fig.1: Next-Gen HBM Architecture Roadmap. Source: KAIST TERALAB, under supervision of professor Joungho Kim
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Semiconductor Engineering published its Manufacturing, Packaging and Materials newsletter this week, featuring these top stories:
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SEMI University published its June 2025 newsletter with updates on new instructor-led trainings as well as on-demand courses. Upcoming trainings include:
A research team at Pasadena City College found a solution to the growing demand for innovative training for future semiconductor engineers, technicians, and scientists by developing AI-powered VR to create learning simulations.
Cadence upgraded its flagship Xtensa LX8 Platform with symmetric multiprocessing capability to ease the programming of multiple DSPs. The new platform will allow SoC designers to automatically generate a cluster of up to eight DSPs devices with hardware cache coherency.
EUV Tech introduced the FALCON Photoresist Flood Exposure Tool, a fully automated EUV metrology system designed for high-throughput resist sensitivity testing and diagnostics.
Infineon introduced a radiation-tolerant memory portfolio for low-Earth orbit missions, which deliver internet access, observations, and weather information back to earth. Infineon also provided its EZ-USB FX10 and FX5controllers to CIS Corporation for its new USB 5 Gbit/s and 10 Gb/s camera for enhanced data transfer and performance.
Nevada-based I/ONX emerged from stealth mode with an AI heterogeneous compute platform, which it said can orchestrate any chipset —CPU, GPU, ASIC, and/or FPGA— within a rack system.
A world record data rate of 280 Gbps in the 300 GHz band was achieved with sub-THz for 6G in a collaboration with Keysight’s vector component analyzer and NTT’s InP-based J-band power amplifier.
University of California San Diego engineers developed a fiber membrane that passively removes heat through evaporation. This could improve the energy efficiency of data centers and high-powered electronics.
Researchers at Penn State created a CMOS computer without silicon, using molybdenum disulfide for n-type transistors and tungsten diselenide for p-type transistors.
Researchers from Northeastern University conducted a two-stage differential temperature sensor study using a chopped cascode transistor technique. The research examined its potential use for anomaly detection in emerging wireless IoT systems.
Find more chip industry research here.
CEA-Leti and Soitec struck a deal to use FD-SOI to secure against physical attacks, from the substrate level up to circuit design.
DARPA and the US Air Force are leveraging formal methods to deploy on the MQ-9 Reaper pilot weapon system program, which will help eliminate exploitable vulnerabilities before software is deployed.
The UK government posted its Cyber Growth Action Plan, including up to £16 million in new investment to boost cyber startups and R&D.
Infineon introduced two new solutions to address the growing demand of electronic IDs (eID), offering local security printers and card manufacturers greater flexibility in selecting the right solution for their specific project requirements.
Recent security research:
CISA issued a number of new alerts/advisories.
NXP completed its acquisition of TTTech Auto, a safety-critical systems and middleware SDV company. NXP also co-developed a centralized vehicle architecture for advanced domain and zonal control with Rimac Technology.
Murata issued a new series of automotive-compliant chip ferrite beads for wide-band noise suppression of high-frequency (5.9GHz) 5G vehicle-to-everything (5G-V2X) applications that exhibit high impedance.
Recent automotive research:
Researchers at MIT’s Plasma Science and Fusion Center created a superconducting circuit claiming it could eventually replace semiconductor components in quantum and high-performance computing systems. The researchers made SD-based superconducting rectifiers that can convert AC to DC on the same chip, allowing for the efficient delivery of the DC current necessary to operate superconducting classical and quantum processors.
DARPA’s new OASIC program is developing advanced quantum testbeds that rapidly test, evaluate, and prototype integrated chip-scale quantum technologies for practical use by smaller businesses.
Canada-based Photonic Inc. will open a quantum R&D facility in the UK.
Funding and projects:
Upcoming webinars are here, including:
Find upcoming chip industry events here, including:
| Date | Location | |
|---|---|---|
| EVENTS | ||
| CadenceCONNECT: Tech Days Europe 2025 | Jun 10 – Jul 3 | Multiple |
| International Symposium on Computer Architecture (ISCA) | Jun 21 – 25 | Tokyo, Japan |
| DAC: The Chips to Systems Conference 2025 | Jun 22 – 25 | San Francisco |
| ALD/ALE 2025 | Jun 22 – 25 | Jeju Island, South Korea |
| Strategic Materials Conference—SMC | Jun 23 – 25 | San Jose, CA |
| 3D & Systems Summit | Jun 25 – 27 | Dresden, Germany |
| ESD Alliance Master Class: Introduction to Chip Design and Electronic Design Automation | Jun 25 | Virtual |
| Inaugural SMART USA Summit | Jun 26 – 27 | Arlington, VA |
| Realize LIVE Europe (Siemens) | Jun 30 – Jul 2 | Amsterdam |
| GSA TECH Summit | Jul 1 | San Jose, CA |
| IMAPS CHIPcon 2025 | Jul 7 – 10 | San Jose, CA |
| SNUG India | Jul 10 | Sheraton Grand Bengaluru Whitefield |
| Semiconductor Ecosystem Overview Virtual Training | Jul 14 – 15 | Virtual (US and EU) |
| Ansys: Simulation World 2025 | Jul 16 -17 | Virtual and some in-person events |
| Understanding Semiconductor Technology and Business | Jul 16 | Virtual (Asia) |
| Overview Of Semiconductor Manufacturing: Virtual Training | Jul 17 – 18 | Virtual (Asia) |
| Smart Manufacturing & AI | Jul 21 – 22 | Virtual (US & EU) |
| Find all events here. | ||
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