Shortages, pricing pressures, rising investments and more packaging options add up to an interesting year for OSATs.
The IC packaging market is projected to see steady growth this year, amid ongoing changes in the landscape.
The outsourced semiconductor assembly and test (OSAT) industry, which provides third-party packaging and test services, has been consolidating for some time. So while sales rising, the number of companies is falling. In late 2017, for example, Advanced Semiconductor Engineering (ASE), the world’s largest OSAT, moved one step closer toward acquiring Siliconware Precision Industries (SPIL), the fourth largest OSAT. In addition, Amkor, JCET and other OSATs recently made acquisitions.
This bodes well for the remaining OSATs, which are coming off a robust year in 2017. The overall outlook for IC packaging is tied to the demand picture in the semiconductor industry. In total, the IC industry is projected to reach $376.9 billion in 2018, up 7.8% over 2017, according to VLSI Research.
That growth will be tempered somewhat, at least for the next few months. Rising demand for chips caused select shortages of manufacturing capacity, various package types, leadframes and equipment. Still, based on the IC forecasts, OSATs are relatively upbeat.
“We’re cautiously optimistic about 2018. It looks like it should be a solid year,” said Scott Sikorski, vice president of worldwide product technology marketing at STATS ChipPAC. “OSAT revenues tend to correlate to IC revenue, specifically IC logic. What you see there is a high single-digit type of forecast for 2018. Of course, memory could be drastically different, much as it was in 2017. Regardless of that, OSATs should then have a similar kind of 2018, which is in that high single-digit range.”
In a preliminary forecast, the OSAT industry is projected to grow from 10% to 12% in terms of revenues in 2017 over 2016, according to Sebastian Hou, an analyst at CLSA. In 2018, though, the OSAT market is projected to cool down and grow 5% to 7%, Hou said.
Fig. 1: Growth rate for OSAT industry. Source: CLSA
As in past years, OSATs face some challenges in 2018. First, they must keep up with the ongoing demand in the industry. Second, they also must continue to develop new and advanced packages. Many IC makers are looking for an alternative from a traditional, leading-edge system-on-a-chip (SoC) design due to cost. One way to get the benefits of scaling is to put multiple devices in an advanced package, which may provide the functionality as an SoC at a lower cost.
But developing these advanced package types, as well as leading-edge SoCs, is becoming more challenging at each node. It requires a huge investment, although ROI is sometimes unclear. “As the system becomes more pervasive, the packaging requirements, the SoC requirements and the SiP (system-in-packaging) requirements need to evolve,” said Tien Wu, chief operating officer at ASE, in a recent presentation. “(These technologies) needs to be cheaper, smaller, more reliable and consume less power. These are the challenges the whole ecosystem and the community are facing.”
The changing landscape
The IC packaging market, which accounts for all package types, was a $54.6 billion business in 2016, growing at a rate of 3.5% from 2016 to 2022, according to Yole Développement.
Advanced packaging is growing faster than the overall market. “If you focus only on advanced packaging, it was a $22.5 billion business (in 2016) and growing at an annual rate of 7% for 2016 to 2022,” said Jérôme Azémar, an analyst at Yole.
In its latest forecast, KeyBanc Capital Markets projects that capital spending for OSATs will reach $2.698 billion in 2017, down 2% over 2016. In 2018, capital spending for OSATs is expected to reach $2.742 billion, up 4%, according to KeyBanc.
“CapEx will be steady from 2017 to 2018,” according to Cristina Chu, strategic business development director at TEL NEXX, which is part of TEL. Advanced packaging, such as 2.5D, fan-out and SiP will “drive the packaging equipment market,” Chu said.
Others agreed. “In this segment, we see ongoing OSAT investment in technology and capacity for advanced packaging, such as fan-out WLP (wafer-level packaging) and 2.5D,” said Stephen Hiebert, senior director of marketing at KLA-Tencor. “Furthermore, we see strong OSAT investment in China as advanced packaging capacities ramp to match Chinese front-end fab projects.”
In addition, IC packaging is no longer driven by just one market. “Rather than being solely focused on mobile, as in previous years, we expect that the packaging equipment business will be driven by a variety of sectors—5G, AI, IoT, automotive and VR/AR,” Hiebert said.
There are other drivers. “Automotive is interesting with the electrification of vehicles and the move toward autonomous driving. In machine learning, there are a lot of packaging challenges. It tends to be very I/O- and compute-intensive,” STATS ChipPAC’s Sikorski said. “The biggest surprise, and the one that’s had the most commercial consequence, is cryptocurrency mining. It has driven a tremendous amount of activity for the foundry and packaging world.”
Bitcoin and other cryptocurrencies are traded and the transactions are recorded on a secure ledger called a blockchain. Then, a third-party, called a miner, verifies the transactions using racks of specialized computers running a hashing algorithm. Each system incorporates anywhere from 100 to 250 ASICs.
Besides the market drivers, packaging customers also need to keep a close eye on the changing OSAT landscape. As before, there are three types of entities that provide chip packages and test services—OSATs, foundries, and integrated device manufacturers (IDMs).
OSATs are merchant vendors. At last count, there are more than 100 different OSATs in the market. A few OSATs are large, but most are small- to mid-sized players.
Fig. 2: Revenue ranking of OSAT providers for 2017 (in US$ millions.) Source: TrendForce
Generally, IDMs develop packages for their own IC products. Some foundries, such as Intel, Samsung and TSMC, provide turnkey chip packaging and test services for customers. Most foundries don’t develop chip packages for customers. Instead, they hand off the packaging requirements to the OSATs.
Regardless, packaging is a tough business. Customers want the OSATs to cut their packaging prices by 2% to 5% every year. At the same time, OSATs are dealing with sharp increases in R&D costs and capital spending. At one time, OSATs could set up a manufacturing line for several million dollars. Today, it costs $100 million to $200 million to build a new manufacturing line for advanced packaging. For this, OSATs must buy a range of new and expensive equipment.
OSATs are investing in new plants. But generally they don’t have deep pockets to invest in every technology because they work on lower margins. So OSATs must spend their R&D dollars carefully to ensure a return. “The transition to newer, high-end packaging solutions drive the need for increased CapEx, which could become a challenge for the OSAT segment,” said Choon Lee, vice president of advanced packaging at Lam Research.
In contrast, the foundries with deeper pockets, such as Intel, Samsung and TSMC, are pouring millions, if not billions, of dollars into IC packaging. Typically, the foundries are developing and offering advanced packages, a move that puts them in competition with the OSATs.
All told, only a few OSATs can afford to make the necessary investments in advanced packaging. In fact, many OSATs are struggling to keep up with the investments required for all package types.
This is becoming a cause for concern in the supply chain. “Underlying semiconductor suppliers, such as wafer substrate suppliers and even OSATs, have not really continued to invest on a regular basis. And with the sustained high demand, these weaker links may now be requiring some support and investment to upgrade and expand,” said Walter Ng, vice president of U.S. sales at UMC. “However, while demand has continued to outstrip supply in many cases, the pricing pressures continue. At some point in the near future, there will be movement to a new equilibrium where investments will need to be made, resulting in higher prices.”
Besides the OSATs, Ng is referring to suppliers of silicon wafers. After years of oversupply, silicon wafer vendors see strong demand. Yet vendors have not invested in new plants, and many have raised their prices.
To solve the issues in the IC packaging supply chain, many of the larger OSATs are consolidating in an effort to combine their R&D and resources. Here are some of the big acquisitions in recent times:
Despite the consolidation, there are still dozens of small- to mid-sized OSATs. But is there still room for them?
“Yes, but the landscape, of course, is ever-changing and challenging. As the customer base consolidates, it’s becoming more challenging to split the outsourcing pie,” said Gil Chiu, vice president of North America at Unisem, a Malaysian-based OSAT. “There are market segments which are better served by the mid-to-large OSATs. Not everyone has the scale (to engage with) mega-OSATs.”
Rush to advanced packaging
Besides the OSAT landscape, the IC packages themselves are also somewhat confusing. Customers can choose between a multitude of packages, including 2.5D/3D, BGA, fan-in, fan-out, leadframe, SiP and many others.
One way to segment the packaging market is by interconnect type, which includes the following technologies—wirebond, flip-chip, wafer-level packaging (WLP) and through-silicon vias (TSVs).
Today, some 75% to 80% of all IC packages utilize an older interconnect scheme called wire bonding, according to TechSearch International.
Developed in the 1950s, a wire bonder resembles a hi-tech sewing machine that stitches one chip to another chip or substrate using tiny wires. Wire bonding mainly has been used for low-cost legacy packages, mid-range packages and memory die stacking.
Wirebond packaging is a big business, as it generates from $13 billion to $15 billion in revenues per year, analysts said. But wirebond is a mature market, projected to grow at a rate of only 2.4% from 2014 to 2019.
That’s why OSATs are rushing into the faster-growing advanced packaging market. In advanced packaging, the main idea is to integrate several dies into the same package to achieve a given function. Integrating several dies in the same package falls under a generic category called multi-die or heterogeneous integration.
For this, there are several packaging options. Generally, though, there is no single package type that can provide all requirements. As before, a customer selects an IC package type based on several factors, such as the application, I/O count, form factor and cost.
“We expect that different advanced packaging technologies will be adopted for different end-user applications,” KLA-Tencor’s Hiebert said. “It’s not likely that one platform will excel on enough dimensions to dominate broadly across all the semiconductor growth markets.”
At the high end, meanwhile, OSATs offer 2.5D/3D technologies, a die stacking technique that promises to boost the bandwidth in devices. In 2.5D/3D, TSVs run through a die or a separate interposer die. In total, the 2.5D/3D TSV market is expected to grow at 28% from 2016 to 2022, according to Yole.
Fig. 3: 2.5D with TSVs and high-bandwidth memory. Source: Samsung
“(2.5D/3D) seems to be taking off,” said Gary Patton, CTO at GlobalFoundries. “If I look at our ASIC design wins over the last year on 14nm, roughly 40% of them have been more than just a wafer. They have included some level of advanced packaging like 2.5D and 3D.”
2.5D/3D technologies, though, are relatively expensive, limiting the market to high-end applications. “2.5D will continue its slow growth in the HPC (high-performance computing) and automotive sectors for specific applications,” said Ron Huemoeller, vice president of research and development at Amkor. “Graphics is a main driver still, but multi-logic configurations will also require 2.5D packaged structures to address the AI market.”
Others are developing 2.5D/3D alternatives. For example, Intel is touting a silicon bridge technology, dubbed Embedded Multi-die Interconnect Bridge (EMIB). In EMIB, the dies are arranged side by side and connected using a small piece of silicon.
SiP is another option. Generally, a SiP combines a series of multiple dies and passives to create a standalone function.
Each technology has its place. “Many of the OSATs are investing in SiP right now,” TEL NEXX’s Chu said. “EMIB will definitely hit the market in 2018. More and more 2.5D will be under development this year, though it will occur in low volumes for niche applications such as FPGAs.”
Fan-out mania
Meanwhile, WLP, perhaps the hottest market, involves packaging an IC while it’s still on the wafer. WLP involves two package types—chip-scale packaging (CSP) and fan-out.
Fig. 4: Comparison of fan-in, flip-chip and fan-out. Source: Yole Développement
CSP is a fan-in technology, where the I/Os are situated over the solder balls in the package. “Fan-in is an increasingly popular package because of the small format,” STATS ChipPAC’s Sikorski said. “The roots of that are in the smartphone market. That continues to be the primary driver. But in IoT applications and wearables that have space constraints, you will see an increase of usage in fan-in.”
Fan-out, though, is generating the most buzz in the market. In fan-out, the interconnects are fanned-out in the package, enabling more I/Os. Fan-out doesn’t have an interposer, making it cheaper than 2.5D. “What’s driving (fan-out) are mobile applications,” said John Hunt, senior director of engineering at ASE, in a recent presentation.
The fan-out market is expected to grow from $244 million in 2014 to $2.5 billion by 2021, according to Yole. “Our estimate for 2018 for the fan-out market is $1.4 billion,” Yole’s Azémar said. “It is a high number, but we justify that because we assume Apple won’t be the only one to have their application processor packaged in fan-out.”
Fig. 5: eWLB packaging. Source: STATS ChipPAC
2016 was a big year for fan-out. First, Apple adopted TSMC’s high-density fan-out package for its application processor in the iPhone 7. In its older smartphones, Apple used the older package-on-package (PoP) technology.
TSMC’s fan-out technology is called InFO. Another type of fan-out technology is called embedded wafer-level ball-grid array (eWLB). And in 2016, the two main eWLB packaging suppliers — STATS ChipPAC and Nanium — were sold out of this package type due to huge demand.
In 2017, though, fan-out went in two different directions. Apple continued to use TSMC’s fan-out technology in its latest iPhones, thereby propelling TSMC’s sales in the arena. But eWLB was generally sold out last year. This prompted customers to look for other solutions, causing a pause in the eWLB market.
“At that point, people became nervous and stopped mapping into it, because there was no assurance of supply. They moved to other wafer-level technologies or flip-chip,” STATS ChipPAC’s Sikorski said.
Recently, though, the eWLB market has rebounded, thanks to several events. First, STATS ChipPAC as well as ASE have expanded their eWLB capacities. Then, Amkor bought Nanium, a move that provided some backing for the fan-out specialist.
“We see the (eWLB) engine percolating again,” Sikorski said. “The design activity heated up in the second half of 2017. That should manifest itself as a solid growth year for 2018.”
Others agreed. “Fan-out will continue to grow as a packaged product in the industry. The adoption rate is accelerating with solid capacity in place to support the technology, especially with the acquisition of Nanium by Amkor and additional capital support,” Amkor’s Huemoeller said. “InFO will continue in its current form as an integrated memory pre-stacked package solution for the Apple processor. Beyond that, it remains to be seen how far the current format will extend.”
Besides eWLB, OSATs are developing other types of fan-out packages, such as high-density fan-out, fan-out PoP, and fan-out SiP. Some are also developing and shipping hybrid or substrate-based solutions. “Fan-out on substrate will be the new ‘hot button’ for the industry,” Huemoeller said. “(It will be) introduced in varying forms from low-density to high-density.”
And if that’s not enough, ASE, Nepes and others will enter the panel-level fan-out market in 2018. Today’s fan-out packages involve packaging a die in a round wafer format. In comparison, panel-level fan-out involves packaging a die on a large square panel.
Fig. 6: Comparison of number of die exposed on 300mm wafer to number of die on panel. Source: STATS ChipPAC, Rudolph
“Everybody is interested in cost. How do we reduce the cost? The way we do that is go from a wafer process to a panel process,” ASE’s Hunt said, adding that panel-level fan-out reduces the cost by 20%.
Clearly, customers will have many fan-out options. But it’s unclear which technologies will ultimately fly in the market.
More shortages
Not all of the action is in fan-out. “In addition, there is an increase in flip-chip and WLP demand for 200mm and 300mm devices,” Lam’s Lee said.
Last year, in fact, there was a shortfall of worldwide 200mm wafer bumping capacity. In wafer bumping, solder balls or copper pillars are formed on a wafer, which provides the electrical interconnects between a die and a substrate.
The shortfall of 200mm bumping capacity impacted the supply of CSPs and RF front-end modules for smartphones. Other packaging types were also in high demand or in tight supply.
The shortages are spilling into 2018. But for how long?
“We anticipate the supply chain is making incremental expansions at bottleneck areas, while managing overall capacity expansions based on equipment lead times,” Unisem’s Chiu said. “We anticipate that each specific area can expect shortages to ease in the first half of 2018.”
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