The goal is to use fab-like methods in the lab, but that’s not easy.
Several chipmakers are making some major changes in the characterization/metrology lab, adding more fab-like processes in this group to help speed up chip development times.
The characterization/metrology lab, which is generally under the radar, is a group that works with the R&D organization and the fab. The characterization lab is involved in the early analytical work for next-generation devices, packages and materials. Using advanced metrology equipment, the lab’s goal is to characterize or gain a better understanding of the make-up of new technologies at the atomic scale. The lab pinpoints defects and other problems in devices, which eventually could boost product yields.
Traditionally, there has been a delineation between the lab and fab, and the two organizations often work in silos. The lab provides analytical capabilities with advanced but slower equipment. The fab, which manufactures the chips, also has advanced metrology tools and other equipment, which tend to have faster throughputs.
For some companies, though, the role of the metrology lab is changing. The devices, packages and materials are becoming more complex, but chip and/or packaging vendors are under pressure to maintain their production schedules or even accelerate them. Otherwise, they may miss the market window.
The lab continues to handle the traditional analytical work, but the fab wants the results much faster. So several chipmakers are implementing more fab-like processes in the lab. For example, Intel is automating some tools, conducting more fab-like measurements, and deploying machine learning techniques. More importantly, Intel’s R&D, lab and fab teams are working more closely together to speed up the characterization process. Intel refers to this as a “holistic measurement strategy.”
“One critical purpose of the lab is to provide fundamental learning to drive data-driven decisions early in the process development cycle, especially as device and process interactions are becoming more complex,” said Markus Kuhn, a technical director and engineering manager at Intel. “The technology challenges are driving the fab to reach for lab capabilities to meet the metrology needs. To meet fab demand, lab capabilities need to improve in regards to automation and productivity.”
Samsung, TSMC and others are moving in similar directions, according to analysts. The goal is to speed up the cycles of learning and beat the competition to the punch. “It’s all about information turns,” said Dan Hutcheson, CEO of VLSI Research. “The faster you can learn, the faster you can get to the next node. It’s whoever gets there first.”
As a byproduct of this shift, chipmakers are seeing a related trend. With devices becoming more complex, they are moving some of the advanced metrology lab tools into the fab. That trend isn’t new and is well documented.
Nonetheless, chipmakers face some challenges. In the lab, they want more automation and hardware improvements with the existing platforms. Tool costs are also an issue in both the lab and fab.
Technology challenges
Basically, a chip consists of three parts — transistor, contacts and interconnects. The transistor serves as a switch for the device. A leading-edge chip incorporates billions of tiny transistors.
The interconnects, which are on top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another. Then, a layer called the middle-of-line connects the transistor and interconnect pieces using tiny contact structures.
Fig. 1: Inside a transistor. Source: Wikipedia
Starting in 2011, chipmakers migrated from traditional planar transistors to finFETs at 22nm. Foundries moved to finFETs at 16nm/14nm. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.
FinFETs are faster with lower power than planar transistors, but they are harder and more expensive to make. As a result, process R&D and design costs have skyrocketed. Now, the cadence for a fully scaled node has extended from 18 to 30 months.
Fig. 2: FinFET vs. planar. Source: Lam Research
Still, fueled by AI, 5G, data centers and mobile apps, chipmakers are migrating to the next nodes. They are ramping up 5nm with 3nm in R&D.
At these nodes, the manufacturing challenges escalate. Other issues are also cropping up. “At bleeding-edge nodes, some of these chips are huge. The reticle field, in some cases, can maybe only sustain a handful of these chips. In some cases, the yields are not very good,” said Walter Ng, vice president of business development at UMC.
Nonetheless, starting at 3nm and/or 2nm, chipmakers plan to migrate from finFETs to a next-generation transistor called nanosheet FETs. A nanosheet FET is a finFET on its side with a gate wrapped around it.
“There is a lot more complexity in a nanowire or nanosheet than in a finFET. There are new processes, and those are very challenging,” said Rick Gottscho, CTO of Lam Research.
The challenges aren’t limited to logic. For example, vendors are shipping various next-generation memories, such as phase-change memory and STT-MRAM. These memories are fast with unlimited endurance, but they require some new innovations to get a bigger foothold in the market.
“Complexity, among other things, will come with the introduction of new materials, particularly for something like the MRAM stack, which is not only complicated, but also sensitive to process conditions, and therefore difficult to etch vertically,” Gottscho said. “That’s why, to date, you don’t see any high-density standalone MRAM. You see it all being embedded into logic, which is a consequence of the materials.”
Fig. 3: MRAM cell. Source: Wikipedia
Then, in R&D, chipmakers are working on other technologies, including 2D materials, carbon nanotubes and complementary FETs. Next-generation packages are also in R&D.
Not all technologies in R&D will make it into production. The eventual winners and losers are determined by cost, functionality and manufacturability.
Inside the metrology lab
For current and future technologies, the characterization lab plays a big role here. The lab is on the front lines. Next-generation chips, packages and materials tend to go to the analytical lab first for characterization and early integration work. At times, the fab may run into problems with a device. So the fab will call on the lab to handle the failure analysis tasks.
The lab uses various metrology and failure analysis equipment. Some equipment is exclusively used in the lab, while others are found in both the lab and fab.
Using these tools, the goal is to characterize the devices and image them at the atomic scale in three dimensions. Take a new transistor, for example. “We’re looking at various functions, interfaces, materials and electrical components of that transistor. We’re trying to engineer gate stacks and the source/drain. We’re looking at alternative channel materials. We’re looking at patterning capabilities and fidelity at the nanoscale. And that’s just the transistor,” Intel’s Kuhn said. “We also want to know where every atom is and what it is. It’s not just where the atom is and what it is, but how is it bonded or what are the implications to the electronic state within that interface or that collection of atoms.”
Traditionally, the lab provides the data and then hands off the results to the fab. Once the devices are in the fab, the lab is less involved.
That’s starting to change at some companies. “The technology challenges with all these new materials and architectures are pushing us. It’s pushing us into being much more fab-like in terms of how we can generate data,” Kuhn said.
In a presentation at the recent Symposia on VLSI Technology and Circuits, Kuhn outlined how the characterization lab is becoming more fab like. They are:
More importantly, the lab is no longer a silo — at least for some. At Intel and others, the R&D teams, as well as the lab and fab, are working closer together to help speed up the process.
Still, the lab and fab are separate and each group has different charters. But to characterize a given device, both the lab and fab generally will segment a device into various categories, such as the dimensions, composition, dopants and strain.
No one metrology tool can handle all requirements. So the lab and fab may require one or more tools for a given category. In the lab some systems are slow, but they still do the job. Others are being automated. Some are still not up to speed.
All labs are equipped with tools for dimensional metrology. For this, a given tool provides the critical dimensional (CD) measurements for devices, such as height, length and width. For CDs, a lab might use the critical-dimension scanning electron microscope (CD-SEM), which takes top-down measurements of structures. They also use optical CD equipment, which utilizes polarized light to characterize devices.
The lab also uses various X-ray metrology systems. Perhaps the most promising and frustrating technology is called critical-dimension small-angle X-ray scattering (CD-SAXS). Using X-rays with wavelengths less than 0.1nm, CD-SAXS makes use of variable-angle transmission scattering techniques from a small beam size to provide measurements.
“CD-SAXS can solve the CD, disorder in the CD, and differences in electron density between layers,” said Joseph Kline, a materials engineer at NIST. “CD-SAXS can also measure buried structures and optically opaque layers.”
Several companies sell CD-SAXS tools, mostly for R&D. Intel, Samsung, TSMC and others have CD-SAXS tools in the lab.
CD-SAXS provides advanced measurements, but it’s too slow and expensive for the fab. The X-ray source is the big issue. It’s not bright or powerful enough, which impacts the throughput. Some but not all of the other X-ray metrology tools face similar issues.
Still, CD-SAXS is making inroads in some applications, such as high-aspect ratio structures in memory. “For memory, the structures are deep. The scattering is good, so there is a clear roadmap to about 1 minute or less per site,” said Paul Ryan, director of product management at Bruker. “For logic, the technique is still in the concept phase. There are expected to be challenges for the X-ray intensity.”
Other lab tools are making more progress, such as APT, SIMS, among others. These systems are widely used in the lab for traditional characterization work.
Generally, in the lab, atom probe tomography (APT) and secondary ion mass spectrometry (SIMS) are used to examine the dopants in chips. Dopants are elements that modify the conductivity in chips. They include boron and phosphorus.
APT also is used for metals, strain and other applications. “APT is the only material analysis technique offering extensive capabilities for both 3D imaging and chemical composition measurements at the near atomic scale, around 0.1 to 0.3nm resolution in depth and 0.3 to 0.5nm laterally,” said David Larson, director of scientific marketing at Cameca.
In APT, a sample is prepared in the form of a sharp needle-shaped specimen. The tip is biased at a high DC voltage on a cryogenic specimen stage in a chamber. “The very small radius of the tip and the voltage together induce a very high electrostatic field at the tip surface, just below the threshold for atom removal by what is called field evaporation,” Larson said. “When the specimen is subjected to laser or, for some materials, voltage pulsing, one or more atoms are evaporated by the high electric field from the surface and projected onto a position-sensitive detector, with up to 80% of the atoms being detected and reconstructed in 3D with sub-nanometer spatial resolution.”
APT isn’t new and been used for years. The next step for APT is a push toward automation and operator-independent data output.
SIMS, meanwhile, is used for dopants and other apps. “When a solid sample is sputtered by primary ions of few keV energy, a fraction of the particles emitted from the target are ionized,” Larson said. “SIMS consists of analyzing these secondary ions with a mass spectrometer. Secondary ion emission by a solid surface under ion bombardment supplies information about the elemental, isotopic and molecular composition of its uppermost atomic layers. The secondary ion yields will vary greatly according to the chemical environment and the sputtering conditions (ion, energy, angle). This can add complexity to the quantitative aspect of the technique. SIMS is nevertheless recognized as the most sensitive elemental and isotopic surface analysis technique.”
SIMS is attempting to move out of the lab. Cameca recently developed a SIMS platform, which can provide process monitoring at line, if not directly in-line, in an automatic mode.
More measurements
Indeed, automation is a big shift in the lab. Generally, in the past, lab tools were manual. Today, some but not all lab tools are being automated to help speed up the process.
The transmission electron microscope (TEM) is one tool that’s being automated in the lab. A TEM is used for dimensional and strain metrology. Strain involves the channel materials in chips.
In operation, a TEM generates electrons and sends them through a sample. The electrons interact with the sample, which provide information about the structure at the nanoscale. However, a TEM is also a destructive technique. A sample is created by cutting part of a device. Chipmakers would prefer not to cut a device in production. That’s why TEMs are found in the lab, but they also are used in the fab to generate reference data.
In the lab, device makers sometimes combine a TEM with a technique called electron energy loss spectroscopy (EELS). In EELS, the system reduces the incident electrons as they pass through the sample, according to EAG Laboratories.
This in turn provides a 3D tomography image. “It provides us with elemental composition and the dimensions,” Intel’s Kuhn said. “What it lacks is bonding. The next step would be to look at EELS, and look at the near edge fine features and near edge structures, and then isolate the bonding. That activity is in progress.”
Besides automation, other fab-like processes are moving in the lab. For example, in the fab, chipmakers use metrology tools with model-based approaches. For this, the tools don’t measure the actual device. Instead, they measure test structures that mimic the device.
In the lab, Intel is implementing this fab-like approach. “There are automation efforts and full wafer capability being developed across lab tools, as well as the emerging use of these techniques like on-die patterned structures,” Kuhn said.
For strain measurements, a device maker might use test structures. For this, the lab may use high-resolution X-ray diffraction (HRXRD) and Raman spectroscopy. HRXRD characterizes single-crystal thin-film materials. Raman spectroscopy identifies chemical structures and compounds. The TEM is also involved here.
“Raman is an optical method. We can back correlate that to what we see in the TEM. The TEM provides a very local picture of the XRD,” Kuhn said. “Raman provides a more comprehensive means of looking at statistically an array in an ensemble of these nanoscale devices and how they are behaving. This allows for process targeting.”
Meanwhile, if that’s not enough, machine learning also is moving to the lab. Machine learning uses advanced algorithms in systems to recognize patterns in data as well as to learn and make predictions about the information.
Chipmakers are combining various tools with machine learning to find and classify defects in chips. “Machine learning can automate choosing the parameters of the model to make it much faster for the human to explore various model forms,” said Aki Fujimura, chief executive of D2S. “Fabs and mask shops also use classical machine learning in the big data analysis of all the operation data available to look for ways to improve yield and prevent downtime.”
So how can the lab can become more engaged with the fab? That’s where hybrid metrology fits in. In hybrid metrology, you take the measurement data from several metrology tools and combine them.
“In hybrid metrology, you can take any tool. It can be in-line, near-fab or in the lab. You take their output, typically using machine learning, to incorporate it into in-line metrology. And what that enables you to do is have that in-line metrology tool extend its capabilities,” Intel’s Kuhn said.
In the fab
Finally, once the devices are characterized and qualified, they move from the lab to the fab. Fabs are automated facilities that process wafers using various equipment in a cleanroom.
It’s a complex process. To make an advanced logic device, the wafer undergoes anywhere from 600 to 1,000 steps, or more, in the fab.
That’s not the only challenge. Logic and memory devices are more complex. The equipment must process smaller and more exact features at each node. And defects might surface during the flow.
So during the flow, a wafer undergoes several inspection and metrology steps in the fab. Take next-generation nanosheet transistors for example. “Nanosheets present big inspection and metrology challenges,” said Mark Shirey, vice president of marketing and applications at KLA, in a presentation at the recent Symposia on VLSI Technology and Circuits. “These 3D structures introduce new buried defects and noise sources. It looks like a combination of optical and e-beam will be needed to inspect these. And in metrology, there is a lot of local variability that needs to be measured with many new measurements.”
Optical and e-beam tools are wafer inspection systems, which find tiny defects in chips. For metrology, chipmakers will use more than a dozen systems for the latest devices in the fab.
For CD measurements, chipmakers use CD-SEMs, OCD, TEMs and other tools. For nanosheets, chipmakers will also use various X-ray metrology tools.
For example, chipmakers use X-ray photoelectron spectroscopy (XPS) in both the lab and fab. “XPS is a surface-sensitive quantitative spectroscopic technique that measures the elemental composition of thin films to determine the composition of materials in devices,” said Kavita Shah, senior director of strategic marketing at Nova.
Conclusion
Clearly, characterizing structures is a challenging process in the lab. It requires a slew of complex measurements.
That’s only half the battle. Now, the lab must learn how to speed up the process. This will take more time and money, if not a new mindset.
This is becoming a requirement, though. Otherwise, chipmakers may end up falling behind in a competitive landscape.
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