tag: Intel

Using Manufacturing Data To Boost Reliability
By Ed Sperling and Ann Mutschler - 07 Dec, 2021 - Comments: 0

As chipmakers turn to increasingly customized and complex heterogeneous designs to boost performance per watt, they also are demanding lower defectivity and higher yields to help offset the rising design and manufacturing costs. Solving those issues is a mammoth multi-vendor effort. There can be hundreds of process steps in fabs and packaging houses. And as feature sizes continue to shrink, ... » read more

Streaming Scan Network: An Efficient Packetized Data Network For Testing Of Complex SoCs
By Siemens EDA - 07 Dec, 2021 - Comments: 0

Originally presented at the 2020 International Test Conference by Siemens and Intel authors, this paper describes the Tessent Streaming Scan Network technology and demonstrates how this packetized data network optimizes test time and implementation productivity for today’s complex SoCs. The author-submitted version of the IEEE paper is reprinted here with permission. Authors: Jean-Françoi... » read more

Success Stories For Packetized Scan Data
By Geir Eide - 07 Dec, 2021 - Comments: 0

Some new design-for-test (DFT) technologies are difficult, expensive, or risky to implement but offer significant benefits. Other technologies are easy to implement but offer minor improvements. The calculation of whether (or when) to adopt new technology includes consideration of the pressures of DFT today—design complexity, the lack of flexibility in hardwiring scan channels, the proliferat... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 03 Dec, 2021 - Comments: 0

Packaging and test Taiwan’s ASE--the world’s largest OSAT--has announced the proposed sale and disposal of equity interests in its subsidiaries, GAPT Holding and ASE (Kun Shan), to Wise Road Capital, a private equity firm based in China. The deal has a value of $1.46 billion. The announcement is related to four ASE assembly and test facilities in China, including Shanghai, Suzhou, Kunsh... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 19 Nov, 2021 - Comments: 0

Chipmakers China’s Tsinghua Unigroup is in trouble. The group is the parent company of China’s YMTC, a 3D NAND supplier, and other chip ventures. It is close to moving into bankruptcy proceedings. Now, a consortium led by Alibaba has emerged as the frontrunner to take over Tsinghua Unigroup, according to a report from Bloomberg. That deal would keep the company afloat, the report said. ... » read more

Outlook: DRAM, NAND, Next-Gen Memory
By Mark LaPedus - 18 Nov, 2021 - Comments: 0

Jim Handy, director at Objective Analysis, sat down with Semiconductor Engineering to talk about the 3D NAND, DRAM and next-generation memory markets. What follows are excerpts of that discussion. SE: How would you characterize the NAND market thus far in 2021? Handy: All chips are seeing unusual strength in 2021, but NAND flash and DRAM are doing what they usually do by exhibiting more e... » read more

Chip Package Co-design and Physical Verification for Heterogeneous Integration
By Technical Paper Link - 12 Nov, 2021 - Comments: 0

Abstract: "Physical verification of components in 2.5D and 3D integrated chips is challenging because existing tool flows have evolved from monolithic silicon design. These components are typically designed on separate technology nodes nearly independent of each other and integrated along the design cycle. We developed an integration and verification methodology with a physical design driven... » read more

Blog Review: Nov. 10
By Jesse Allen - 10 Nov, 2021 - Comments: 0

Cadence's Paul McLellan listens in as Malcolm Penn of Future Horizons explains key reasons behind the cyclical nature of the semiconductor industry and how the root of the current chip shortage problems goes back to before the pandemic. Siemens EDA's Ray Salemi continues investigating using Python for verification with a look at some UVM utilities and how they would be used in Python. Syn... » read more

More Errors, More Correction in Memories
By Bryon Moyer - 09 Nov, 2021 - Comments: 1

As memory bit cells of any type become smaller, bit error rates increase due to lower margins and process variation. This can be dealt with using error correction to account for and correct bit errors, but as more sophisticated error-correction codes (ECC) are used, it requires more silicon area, which in turn drives up the cost. Given this trend, the looming question is whether the cost of ... » read more

Manufacturing Bits: Nov. 2
By Mark LaPedus - 02 Nov, 2021 - Comments: 0

IRDS lithography roadmap The Journal of Micro/Nanopatterning, Materials, and Metrology (JM3) has published a paper that outlines the lithography roadmap and the various challenges for the next 15 years. The paper, called the "International Roadmap for Devices and Systems lithography roadmap," projects that extreme ultraviolet (EUV) lithography and a next-generation version will remain the m... » read more

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