Research Bits: Dec. 18


Stacking 2D layers for AI processing Researchers from Washington University in St. Louis, MIT, Yonsei University, Inha University, Georgia Institute of Technology, and the University of Notre Dame demonstrated monolithic 3D integration of layered 2D material, creating a novel AI processing hardware that integrates sensing, signal processing, and AI computing functions into a single chip. Th... » read more

Chip Industry’s Technical Paper Roundup: October 24


New technical papers added to Semiconductor Engineering’s library this week. [table id=157 /] More Reading Technical Paper Library home » read more

Scalable And Compact Multi-Bit CAM Designs Using FeFETs


A technical paper titled “SEE-MCAM: Scalable Multi-bit FeFET Content Addressable Memories for Energy Efficient Associative Search” was published by researchers at Zhejiang University, China, Georgia Institute of Technology, University of California Irvine, Rochester Institute of Technology, University of Notre Dame, and Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of ... » read more

Chip Industry’s Technical Paper Roundup: October 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=150 /] Related Reading Technical Paper Library home » read more

LLM-Aided AI Accelerator Design Automation (Georgia Tech)


A technical paper titled “GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models” was published by researchers at Georgia Institute of Technology. Abstract: "The remarkable capabilities and intricate nature of Artificial Intelligence (AI) have dramatically escalated the imperative for specialized AI accelerators. Nonetheless, designing these accele... » read more

Chip Industry’s Technical Paper Roundup: August 22


New technical papers added to Semiconductor Engineering’s library this week. [table id=129 /]   More Reading Technical Paper Library home » read more

Flexible Hybrid Electronics: Future Standards For Next-Gen 5G/mmWave Wearable and Conformal Applications


A technical paper titled “Additively manufactured flexible on-package phased array antennas for 5G/mmWave wearable and conformal digital twin and massive MIMO applications” was published by researchers at Georgia Institute of Technology. Abstract: "This paper thoroughly investigates material characterization, reliability evaluation, fabrication, and assembly processes of additively manufa... » read more

Chip Industry Technical Paper Roundup: August 15


New technical papers added to Semiconductor Engineering’s library this week. [table id=128 /] More Reading Technical Paper Library home » read more

Week In Review: Auto, Security, Pervasive Computing


Intel issued an advisory of a potential security vulnerability in some of its processors. The company recommends updating to the latest firmware version. NVIDIA unveiled its GH200 Grace Hopper platform, based on 144 Arm Neoverse cores and 282GB of HBM3e memory. Meanwhile, Chinese internet companies including Baidu, ByteDance, Tencent, and Alibaba ordered about $5 billion worth of A800 proces... » read more

A RISC-V Capability Architecture Orchestrating Compiler, Architecture, And System Designs For Full Memory Safety (Georgia Tech, Arm Research)


A technical paper titled “RV-CURE: A RISC-V Capability Architecture for Full Memory Safety” was published by researchers at Georgia Institute of Technology and Arm Research. Abstract: "Despite decades of efforts to resolve, memory safety violations are still persistent and problematic in modern systems. Various defense mechanisms have been proposed, but their deployment in real systems re... » read more

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