Gearing Up For Next-Gen Power Semis


After years in R&D, several vendors are moving closer to shipping power semiconductors and other products based on next-generation wide-bandgap technologies. These devices leverage the properties of new materials, such as aluminum nitride, diamond, and gallium oxide, and they are also utilized in different structures, such as vertical gallium-nitride power devices. But while many of thes... » read more

What’s Changing In DRAM


Most of the attention in chip scaling has been focused on logic and on-chip memory, but off-chip memory is starting to encounter problems, as well. David Fried, vice president of computational products at Lam Research, looks at the impact of shrinking features and increasing density, including variation, thermal effects and aging, as well as effects such as micro-loading and DRAM stacking. » read more

Evaluating The Impact Of STI Recess Profile Control On Advanced FinFET Device Performance


In this paper, a 5nm FinFET flow was built using the SEMulator3D virtual fabrication platform. Different STI (shallow trench isolation) recess profiles were investigated using the pattern-dependent etch capabilities of SEMulator3D, including changes in trenching/footing profile, fin height and imbalance fin height. The impact of STI recess profile on device performance was then investigated usi... » read more

Blog Review: Sept. 15


Synopsys' Ian Land and Ricardo Borges examine how radiation modeling can help ensure semiconductor components will survive while housed in equipment that is orbiting our planet or traveling through deep space over extensive periods of time. Siemens EDA's Rich Edelman explores why writing coverage is an art requiring imagination, practice, and patience, along with some tips on how to improve.... » read more

Week In Review: Manufacturing, Test


Chipmakers, OEMs Intel plans to establish foundry capacity at its fab in Ireland. The company has also launched the so-called Intel Foundry Services Accelerator to help automotive chip designers transition from mature to advanced nodes. The company is setting up a new design team and offering both custom and industry-standard intellectual property (IP) to support the needs of automotive custom... » read more

Making Test Transparent With Better Data


Data is critical for a variety of processes inside the fab. The challenge is getting enough consistent data from different equipment and then plugging it back into the design, manufacturing, and test flows to quickly improve the process and uncover hard-to-find defective die. Progress is being made. The inspection and test industry is on the cusp of having more dynamic ways to access the dat... » read more

Blog Review: Sept. 1


Arm's Fernando Garcia Redondo, Pranay Prabhat, and Mudit Bhargava continue their exploration of MRAM simulation by explaining stochasticity experiments and a characterization framework that focuses on the MRAM behavior statistical analysis. Siemens EDA's Neil Johnson shows how performance profiling can be used to identify testbench code that could slow down simulation and when to start using i... » read more

Week In Review: Manufacturing, Test


Chipmakers, OEMs Reports have surfaced that TSMC has delayed its 3nm process. But TSMC says the technology remains on track. Volume production for TSMC’s 3nm is still scheduled for the second half of 2022. On the flip side, there is speculation that TSMC may increase its wafer prices by up to 20%, according to a report from the Taipei Times. Here's another report. This is due to chip shortag... » read more

Blog Review: Aug. 25


Arm's Fernando Garcia Redondo, Pranay Prabhat, and Mudit Bhargava introduce an open source framework and compact model for the simulation, characterization, and analysis of MRAM magnetic tunnel junctions. Siemens EDA's Chris Spear continues the tutorial on SystemVerilog class variables with a look at how to use the $cast() system task to copy between base and derived class variables. Syno... » read more

Advancing To The 3nm Node And Beyond: Technology, Challenges And Solutions


It seems like yesterday that finFETs were the answer to device scaling limitations imposed by shrinking gate lengths and required electrostatics. The introduction of finFETs began at the 22nm node and has continued through the 7nm node. Beyond 7nm, it looks like nanosheet device structures will be used for at least the 5nm and probably the 3nm nodes. The nanosheet device structure is the brainc... » read more

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