7nm Power Issues And Solutions

Design success starts with predictable and reliable RTL To GDS methodology.

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Being able to achieve 35% speed improvement, 65% power reduction and 3.3X higher density makes adopting a 7nm process for your next system-on-chip (SoC) design seem like an easy decision. However, with $271 million in estimated total design cost and 500 man-years it would take to bring a mid-range 7nm SoC to production, companies need to carefully weigh the benefits against the cost of designing at this advanced technology node. In order to make a profit, design teams need to manage cost and resources, and to ensure first silicon success. These considerations are mandating a shift in design methodology toward early analysis, which can influence better downstream decisions and catch design issues in a timely manner.

Managing power consumption and power noise continue to be huge concerns for designs at smaller nodes, and they are key requirements for mitigating design failures. Higher device capacitance, interconnect resistance, and current densities at 7nm finFET nodes underscore the importance of dynamic power and thermal management. By adopting a predictable and reliable RTL methodology, you can identify and fix areas of potential power issues earlier in the process and make better design decisions.

Make early design decisions
RTL power analysis enables high-impact power-related decisions early in the design flow by providing a more intuitive environment for identifying, debugging and fixing potential power issues. Compared to the several hours it takes to synthesize the design and to compute gate-level power, RTL power analysis can be completed within minutes. It is also much easier to simulate design activity at RTL for high coverage. All these benefits allow you to explore multiple architectures for best design decisions across various modes of operation. Driven by rigorous tracking of RTL power across different bandwidth scenarios, AMD noted in a recent ANSYS Advantage article how they reduced power by 70% in a high-performance computing design application.

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Figure 1: RTL power exploration across different bandwidth scenarios for high-impact reduction (Source: ANSYS Advantage)

Accurately predict power
To enable early design decisions, RTL results should reliably predict the implemented design’s final power consumption. This requires a tight link between RTL and physical design for modeling actual physical design details such as clock distribution network, net capacitance, buffers and glitch, while still operating at the RTL level. The predictability and accuracy of RTL power is especially critical for clock nets. Advanced nodes require RTL clock power modeling to take into account the physical structure, timing and power constraints, and interconnect capacitance of the clock nets. Glitch power also has significant impact on the accuracy of the predicted power, and therefore requires RTL modeling and analysis of the propagation of glitch generating logic path. By performing physically and timing-aware clock tree synthesis (CTS), modeling and simulating glitch power, and modeling wire capacitances and other physical effects, you can predict their impact on overall power and make early design decisions with confidence.

Eliminate redundant activity
Eliminating redundant switching is a key component of managing dynamic power. Clocks are high-switching nets with the largest drive loads and control a significant portion of the overall power. Glitch power can constitute 20% to 30% of the total logic power, especially in compute intensive designs. RTL power efficiency metrics are an effective method for you to understand such areas of wasted power. Working on RTL provides the visibility needed for activity correlation between clock, control and data signals on a per-cycle basis, which is necessary for accurate memory and clock gating efficiency analysis.

Complementing downstream tools, RTL-based power simulations also enable complex analyses for automated identification of RTL changes for clocks, sequential logic, and glitch-prone datapath logic to address wasted activity. Working at a higher design abstraction level, RTL provides the capacity to analyze large designs so power that is wasted from the interactions between blocks also can be isolated. This is something that is not possible with implementation tools. In fact, NXP noted in an ANSYS webinar how they were able to utilize RTL power analysis and reduction to debug and fix noise interference from digital logic, which was affecting analog components in their automotive infotainment application.

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Figure 2: NXP utilized RTL power methodology to reduce digital noise interference (Source: ANSYS)

Profile real application activity
Power behavior is highly dependent on the chip activity. Traditional methodologies of identifying appropriate activity modes focus on short-duration windows for power analysis, and they run the risk of missing power-critical events that may occur when the chip is exposed to its real activity. Having early visibility into power and thermal profiles of real-life applications, such as operating system (OS) boot up or high definition video frames, can help you avoid costly power-related surprises late in the design process. Specialized hardware, such as an emulator, can simulate at a much higher speed, which makes analysis based on real-life applications possible. However, running cycle-by-cycle power analysis of such real application activity can be very compute-intensive and can take up to days or even weeks.

Using a high-performance RTL simulation engine, you can generate an accurate per-cycle power profile for very long vectors that is several orders of magnitude faster than traditional methods. This makes it possible to compute power of a high-definition video frame comprising tens of milliseconds of activity within hours, as well as to analyze power profiles for operating system boot-up comprising hundreds of milliseconds of data within a day. Direct streaming of switching data from an emulator into the RTL engine also optimizes runtimes by 5X to 10X.

Drive early power noise and thermal analysis
The ability to quickly run thousands of RTL vectors with millions of cycles of activity provides several key insights. It identifies event activities such as peak switching power (di/dt) that cause large power noise and thermal hotspots. By focusing on power-critical activity areas, you can improve productivity and coverage of transient power delivery network analysis and mitigate risks of design failure. RTL chip current profiles based on real application activity also enable early and accurate co-design of the chip, the package and the board. At the system level, power consumption can have a direct impact on the thermal performance. Understanding power profile throughout the duration of real life simulation helps you determine and address areas of the design that are consuming most power and in turn causing thermal issues.

Track power via regressions
Monitoring power data throughout the design process ensures that downstream design changes do not inadvertently affect its power performance. Power regression provides feedback on the effectiveness of various power reduction efforts and tracks power efficiencies across multiple operating modes. Being able to query the database and compare results across multiple design versions allow you to avoid unfortunate surprises caused by subsequent design changes.

Manage large designs
As the chip size and its functionality continue to grow at an exponential rate, the ability to manage capacity while thoroughly analyzing multiple operating scenarios will become important success criteria. Applying emerging technologies such as elastic computing and big data analytics to RTL power analysis can help manage such complexities.

In summary, power continues to be the leading design challenge at 7nm. In order to successfully deliver designs at this advanced node, you will need to adopt early analysis to:

• Accurately predict power consumption with physical design consideration
• Uncover high-impact power reduction opportunities and eliminate wasted activity
• Increase coverage for power noise and thermal analysis by profiling power across real applications
• Monitor power efficiency across design changes and operations
• Leverage capacity and performance of elastic computing and big data analytics

Deploying a predictable and reliable RTL power methodology can help you achieve faster design convergence.