What’s in store for chipmakers at 7nm, 5nm and beyond, and why atomic-level etch and deposition are getting new attention.
Prabu Raja, group vice president and general manager for the Patterning and Packaging Group at Applied Materials, sat down with Semiconductor Engineering to discuss the trends in patterning, selective processes and other topics. Raja is also a fellow at Applied Materials. What follows are excerpts of that conversion.
SE: From your standpoint, what are the biggest challenges?
Raja: There are a lot of changes happening now. You have transistors, gate-all-around and other things. But the industry has a path to do that. They can go to finFETs or can take an alternate path of gate-all-around. But patterning seems to be the biggest roadblock right now from everything we hear. This is because EUV has been delayed.
SE: Let’s say extreme ultraviolet (EUV) lithography is inserted at 7nm and/or 5nm. Will it solve all of the patterning problems?
Raja: Even if EUV comes in, it might be used for one or two passes. And even if EUV comes in, it’s not for lines. It’s only for cuts and vias. If you really look at the total patterning market, the cuts and vias are maybe only 20% of the total market. The remaining 80% is for the lines and the rest.
SE: So even with EUV, chipmakers will still need to implement a conventional multi-patterning scheme in the flow at 7nm and beyond, whether that’s for lines/spaces and other parts of the structure, right?
Raja: You will still need double patterning and quad patterning.
SE: What are the other challenges?
Raja: When you talk about conventional patterning, multi-patterning seems to be the biggest challenge right now. There are a lot of issues that come out of this. Moving beyond that, when you go to 5nm or 7nm, overlay becomes a bigger issue. The layer to layer overlay becomes a big issue. That cannot be solved with EUV. EUV will enable finer layers. But when you have layer to layer, and then try and connect them, this becomes a much bigger issue. We call it edge placement error. Some people call it alignment. Some people call it overlay. That seems to be the next big challenge right now.
SE: So EUV may solve the resolution issues, but it doesn’t address overlay or the ability to align the various mask layers accurately on top of each other. But clearly, the industry wants EUV, right?
Raja: The industry wants to make EUV happen. But they have challenges to make EUV work right now. There are cost issues. There are defects issues and pellicles. It is not ready.
SE: Many say EUV could get inserted at 7nm and/or 5nm. Any thoughts?
Raja: In some cases, for 7nm, the primary approach could be without EUV. They also may bring in a back-up approach for a ‘7nm-plus’ node. They will test out a couple of layers for EUV. So moving forward, they can use EUV for more than two steps.
SE: At 5nm, chipmakers might require EUV plus a multi-patterning scheme. But let’s say EUV gets delayed again or doesn’t work at 5nm. Then, the industry is talking about self-aligned octuple patterning (SAOP). But SAOP also presents huge overlay issues—it may not work. What happens then?
Raja: When you go beyond SAQP, say SAOP, customers are starting to look at alternative paths right now. They are asking: ‘Can we do something different? Can you provide better performance? At the same time, can you do it with a fewer number of steps?’ That’s where we come in. We come in with new capabilities and materials. The new capabilities involve how to remove materials with selective removal. You also have selective deposition. These can change the way they design the process and reduce them to fewer steps. It also could have a significant benefit in terms of alignment, pitch walking and other capabilities.
SE: Now, you are talking about selective processes like removal and deposition. These technologies won’t replace traditional lithography. But how do these selective technologies change things?
Raja: The difference is that the industry can introduce new materials they have no experience with. When you introduce new materials, you need to put in new removal steps and new clean steps. It’s a bigger change in the scheme. It’s a completely different way of looking at the problem.
SE: Let’s first talk about selective removal, sometimes called atomic layer etch (ALE). ALE has been in R&D for several years, but the technology is finally here. Selective removal is a complementary technology. What is selective removal?
Raja: In selective removal, you remove certain materials. Typically, you have multiple steps to remove one material. We can remove one material without touching the other materials.
SE: Where is this technology being used?
Raja: Selective removal can be used across a number of applications. The main application is multiple silicon removals. That’s where we started. It’s already in production right now or pilot production. Now, we are already qualified for oxides. We are being qualified for nitrides. We are being qualified for metal oxides right now. It is expanding into more and more materials right now. It mainly started with logic. Memory is getting in right now.
SE: Can you give us an example of how this is used?
Raja: The idea is we can do anything based on what chemistry we choose and how we do it. Here’s a simple example. Let’s say you have an alternating stack of silicon and silicon germanium. This is a horizontal etch. Without touching silicon, we can remove only the silicon germanium. If you look at the soft corners, we don’t even touch it. That was not possible before. At the same time, we can do SiGe without touching the silicon. The same tool can do it.
SE: I assume this is a slower process, as compared to traditional etch, right? What are the dimensions of these selective removals?
Raja: This is a slow process. But this could be 2nm or 3nm. We can control it to the 10 angstrom level of removals, even less than that. Normally, people want to address very soft and very critical areas. They can use this process.
SE: The example you presented sounds like an application for a gate-all-around FET, a next-generation transistor type that is targeted for 5nm. Will the industry extend the finFET or move to gate-all-around at 5nm?
Raja: People are looking at both. Which way are they going? It remains unclear.
SE: Can you give us another example of what you can do with selective removal?
Raja: Customers are coming back and saying: ‘On top of this material removal, I want to remove only the bottom and top material (in a trench). So we not only want to do material-to-material selectively, but we also want material selectively, plus geometry selectively.’ We can do it right now.
SE: What’s the value in that?
Raja: Suppose somebody wants to grow only on the side. Suppose you want to have a spacer. You can do that.
SE: Let’s switch gears. For decades, chipmakers have used traditional deposition. Meanwhile, in R&D, the industry for some time has been exploring a novel technology called selective deposition. Using Atomic Layer Deposition (ALD) tools, selective deposition involves a process of depositing materials and films in exact places. Where is selective deposition now?
Raja: It’s in the R&D stage. People have been talking about it for a long time. Some metals have always been possible. Cobalt was possible a few years back. Epi was possible a few years back. The dialectic was always the biggest challenge. The question is how you grow dielectrics. A breakthrough has happened very recently from our side. We are starting to see that we know how to grow this.
SE: But are chipmakers interested in selective deposition?
Raja: For the last four to five years, we’ve talked about it. But there was not a real desperate pull from our customers. Now, when you look at this, and you go to 5nm and 3nm, you know that you will be in trouble without it. So we are starting to put our focus on that.
SE: Do you need customized ALD tools to enable selective deposition?
Raja: Regarding the tool sets, they are not a lot different than what we have already. It’s really all about playing with the chemistries and materials. Once you have figured out what to do with the chemistries and materials, the tool set is not the challenging part. We can just plug it into our current tool set.
SE: Intel, for one, is pushing selective deposition. They say selective deposition could potentially solve one of the biggest roadblocks in chip scaling—edge placement error (EPE). EPE is measured as the difference between the intended and printed features in a layout. To solve the EPE problem, according to Intel, a futuristic tool selectively deposits a tiny metal strip between two lines in a pattern. In effect, the metal strip acts as a guide between the two lines, preventing a misalignment in the patterning process. Is that the main app for selective deposition?
Raja: It’s one of them.
SE: What are the other apps?
Raja: On the transistor side, people are interested in it. On the pattering side, people are interested. Even for the backend-of-the-line, it could be used. There are multiple places you use it.
SE: When will the customer base use selective deposition?
Raja: Can we do it by 5nm or 7nm? We don’t know yet, because it’s an alternative path. People have to think differently. The device scheme has to change for it. If they use it, how many steps will they use? We don’t know that right now.
SE: What are the challenges with selective deposition?
Raja: The challenge that we had before is that the chemistries don’t like each other. We call it incompatible chemistries.
SE: How do you solve this?
Raja: The new capabilities we are bringing to the market completely isolate the chemistries. Even though it’s the same chamber, the chemistries don’t mix at all.
SE: Where is this all going?
Raja: There are multiple places you can do selective deposition. People have been thinking about it a long time. So they know where they want to use it. Regarding selective removal, no one was dreaming about it. So once they know how to use selective removal, now they are thinking: ‘You can do selective deposition and can combine it (with selective removal).’