Multi-Patterning Issues At 7nm, 5nm

Variations in different masks, alignment problems and the physical limits of immersion add up to serious issues at 7nm and 5nm.

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Continuing to rely on 193nm immersion lithography with multiple patterning is becoming much more difficult at 7nm and 5nm.

With the help of various resolution enhancement techniques, optical lithography using a deep ultraviolet excimer laser has been the workhorse patterning technology in the fab since the early 1980s. It is so closely tied with the continuation of Moore’s Law that it is difficult to think of one without the other. But how much longer this technology can continue isn’t clear, given the magnitude and breadth of the problems expected at upcoming nodes.

The semiconductor industry has been banking on extreme ultraviolet (EUV) lithography for the past decade to circumvent the problems that 193i is beginning to encounter. For example, immersion lithography requires double patterning at 16nm/14nm and quadruple patterning at 7nm. Both schemes work, but they present some new and major challenges. Extra patterning increases the cycle time and cost in both the photomask shop and in the fab. And that’s just the tip of the iceberg.

But if chipmakers extend immersion/multi-patterning to 5nm, they may need to resort to the unthinkable—octuple patterning, described almost universally as a nightmarish scheme that is considered unwieldy and too costly.

At 7nm and/or 5nm, the alternative is EUV, which supposedly simplifies the patterning flow. With a 13.5nm wavelength, EUV would be able to pattern even the finest detail with a single pass at a 22nm half-pitch. If EUV is ready, chipmakers likely would use EUV to pattern some of the critical features, such as contacts and vias, at 7nm with a single exposure. But at 5nm, they would require EUV, plus a multiple patterning scheme.

Still to be seen, however, is when or whether EUV will become commercially viable. And given the uncertainty with EUV, the industry must continue to develop multi-patterning as a backup plan at 7nm and/or 5nm. It might even end up as the primary option at those nodes. If so, octuple patterning would become a reality.

Already, more problems are beginning to surface with 193nm immersion. For example, when wires and devices are split into two or more masks using quadruple or octuple patterning, it can affect the overall performance of a chip as well as the yield.

Variation is another issue. “The challenge at every new node is to understand how the specs are printed,” said Carey Robertson, product marketing director for Calibre extraction at Mentor Graphics. “They are never printed at the exact number. And as you entertain other structures, the deltas will be non-intuitive. The problem is understanding what the metal will actually look like because one mask has a different variation than another.”

That issue grows worse with each new node after 22nm. With quadruple patterning, for example, printing wires or devices is more difficult than with double patterning. There are more masks required. Then, the masks must be broken into different pieces, which in turn are layered on top of each other.

screen-shot-2016-11-27-at-1-24-20-pm
Fig. 1: Double patterning scheme. Source: Mentor Graphics.

“So how does this transistor perform differently from one version to another? With 16/7/5nm device models, you need to reinvent it each time,” said Robertson. “There are well proximity effects to deal with and stress effects in the silicon.”

And then there is the problem of overlay, which involves the ability of a scanner to align the various mask layers accurately on top of each other. Overlay has its own set of issues, ranging from line-edge roughness to alignment. If mask alignment is off by just 1nm it can alter the electrical characteristics of a device, affecting everything from performance and power to the integrity of the signals.

“Overlay is becoming increasingly difficult,” observed Aki Fujimura, CEO of D2S. “Registration markers, for example, need to be increasingly more precisely written and read, in addition to all of the writing tools needing additional positional accuracy over the whole printing surface.”

This has an impact upstream, as well, particularly at the floor-planning stage in the design process. At older nodes, it’s okay to mix and match structures. But at advanced nodes, those structures need to be lined up more carefully to account for what happens later in the flow on the manufacturing side. And downstream, more rigid design rules define what can be done upstream, which affects everything from IP and memory choices, how signals are routed, as well as how much differentiation there is between chips from different chipmakers.

“This is definitely a part of the reason for the need to be more precise in the placement of every feature on each mask,” said Fujimura. “It isn’t enough to have the right critical dimension of a feature. You have to have it in the right place. The increase in the number of exposures per layer makes this increasingly difficult.”

Variation issues
Process variation has become more troublesome at each new process node. It affects basic dimensions of any device, and it gets progressively worse as the dimensions of those devices continue to shrink—and more difficult to pinpoint problems when they occur.

“There’s an averaging issue because you have to deal with a fairly long trace,” said Greg Yeric, an ARM fellow. “You may have a misalignment of a pattern in the die. In the era of severe multi-patterning, you could have three or four misalignment issues, which could affect capacitance and yield.”

While existing design-for-manufacturing (DFM) tools take that kind of variability into account with a reasonable amount of accuracy, the number of corner cases increases at each node. Those typically are addressed by adding extra circuits, or margin, into a design. But at advanced nodes, margin can have a big impact on performance and the power necessary to drive signals through longer and skinnier wires. It also can change the thermal characteristics of a design, which is particularly troublesome in the finFET world due to higher dynamic power density.

“With 7nm and 5nm, the fin height is higher, so the amount of heat that gets trapped is higher,” said Norman Chang, vice president and senior strategist at ANSYS. “You also have more and more wires that can interact in terms of thermal migration. Within one nanometer, heat can propagate to another wire. If you look at the channel bus, there are lots of wires within one small area. With the thermal migration effect, local temperature can be higher than expected.”

This kind of issue was treated separately from the manufacturing side in the past. But at advanced nodes, many of these issues converge in ways that various parts of the design through manufacturing chain never considered before. And they are made worse by variation caused by multi-patterning.

“Double patterning and quadruple patterning add an extra component of variability,” said Jamie Schaeffer, director of FDX product line management at GlobalFoundries. “There is variability of misalignment built in for worst-case corners. So at 7nm, backend-of-line capacitance is excessive. RC delay is a huge performance limiter there versus 14nm and 28nm.”

It becomes more difficult to spot those variations, too, because in a 7nm structure not all of the wires are exposed in different masks, and not all of the interactions are obvious.

“The variations are highly nuanced,” said David Fried, chief technology officer at Coventor. “They may include the mandrel, the cut and the via. And the interconnect is the product of multiple masks, so you may have a complicated data path from metal 2 to 3 to 4 and back to 2—and you’re dealing with interactions on wires from 15 different masks, all with more variations. You really need to understand the manifestations of process variation on the final structure, and that’s hard because many of the effects are statistically non-correlated.”

So even though a critical dimension variation may not affect line-end exposure, it has to be treated as an unknown corner because it may not be correlated as a fast wire or a slow wire corner. “This is a huge problem and it gets insanely complicated,” Fried said. “You need to go through a mass problem of 180 possible processes contributing to wire-line variation. CD budgets are plus or minus 1.5nm. Overlay is plus or minus 2nm.”

What’s after 193i?
EUV can help considerably at 7nm, and both Intel and Samsung are betting on it for that node. TSMC and GlobalFoundries are not planning to insert it until 5nm—a determination that likely will depend on a variety of issues ranging from cost to the availability of pellicles, actinic inspection of EUV masks, and the quality of photoresists.

“Considering density enhancement, process simplification and cycle time, EUV technology is expected to be a better lithography solution for 7nm and beyond,” said Yan Qu, senior regional marketing manager at UMC. “Plenty of industry efforts are still under way to bring EUV to mass-production. But 193 immersion has become an alternative approach because the maturity of EUV is still behind schedule for 7nm production. Next-generation 193i exposure tools with novel reticle enhancement techniques, inverse lithography technology and optical proximity correction, as well as advanced overlay control methodology, are under development for 7nm. Nevertheless, the challenges of more rule constraints on circuit design are inevitable, in addition to defect control.”

There are questions about whether multi-patterning will be required with EUV, as well. At this point, there are no clear answers.

“The world hopes EUV doesn’t require multiple patterning for a while,” said D2S’ Fujimura. “But the need for precision on the mask is even greater with EUV than with 193i. 193i is blind to small differences on the mask. So long as the local average of the energy and position projected through the mask is preserved, small perturbations aren’t ‘seen’ by 193i. EUV can see a lot better. So it will more accurately reflect the undulations that exist on the mask onto the wafer.”

Mask-writing is straightforward using orthogonal, or axis-parallel, straight edges on the wafer, he explained, but it does take longer. There are more features on the same mask, and slower resists need to be used to write the smaller features on the mask accurately and reliably.

“Depending on the data size, multi-beam mask writers may be superior for these types of masks,” Fujimura said. “Mask inspection and repair will be more difficult with EUV masks because smaller defects will need to be found and repaired to prevent those defects from appearing on every chip of every wafer for that layer.”

Directed self-assembly may play a role here, as well. Industry insiders, who spoke on condition they not be named, said the real play for DSA in the short term may be less about patterning than pattern healing. DSA’s expected insertion point for patterning, in contrast, may be at 3nm—if that node ever happens.

Self-aligned schemes are gaining attention, too, particularly for vias. Self-aligned double patterning and quadruple patterning use one lithography step followed by deposition and etch steps to define features. A mandrel is formed on a substrate, then material is deposited on that layer and etched to form spacers.

fig4_sadp_metal_process-1024x741
Fig. 2: SADP Metal Process where spacer is dielectric. Source: Mentor Graphics.

In the fab, the big challenge is to execute a multi-patterning scheme with precision. In SAQP, for example, the spacer-based mandrel has three separate critical dimensions (CDs). Each mandrel must be identical in terms of CDs. If they don’t match, there are unwanted pitch walking and variability issues in a device.

“One of the ways to mitigate problems is to use self-aligned vias early on,” said ARM’s Yeric. “The via is aligned to the metal edge on the top of a line, and it can be self-aligned on the bottom. That makes it immune to a shorting problem. So a fully aligned via is one thing. Another improvement will be air gap. Intel is claiming a 17% capacitance improvement using air gapping. Outside of Intel no one is seeing that kind of number, but it does provide good resistance amelioration.”

All of this requires changes in the design through manufacturing flow, though.

“We’re also going to see DFM take on a more detailed role in getting into the blood and guts of every via,” said Coventor’s Fried. “DFM has to reach down deeper. We’ve automated design systems for ultimate density and fastest time to solution. But now the design side is light years ahead of the process. DFM is one leg that needs to be strengthened.”

Other issues
Multi-patterning brings in yet other issues, too. For one thing, there are simply too many masks at each new node. That slows down throughput in the mask shop, increases the possibility that errors will be introduced, and raises the cost. It is estimated that EUV will trim between 9 to 12 lithography steps at 7nm, compared with 34 using 193i.

Multi-patterning also reduces the possibility of second-sourcing derivative designs. “You’re not going to ship ‘Design A’ off to one foundry and ‘Design B’ off to a different foundry,” said Michael White, director of product marketing for Calibre Physical Verification at Mentor Graphics. “For one thing there are unique models for each foundry. For another, the masks are broader that you’re modeling for. And with multi-patterning, that becomes too hard.”

White noted that of the 90 companies moving to advanced nodes, 35 of them already are doing some form of multi-patterning at this point. They all will be doing multi-patterning by 7nm.

Conclusion
In light of these issues with multi-patterning, even the most stalwart critics of EUV are hoping it successfully gets deployed at 7nm and 5nm. DSA utilization will continue to grow, and there may be an opportunity for next-generation lithography, including multi-beam e-beam, complementary e-beam lithography and nanoimprint.

But at least in the short term, 193i has run so far past its expected life—and its realistic capabilities—that it is becoming less of a well-known and trusted solution and more of a troublemaker that needs an increasing amount of attention. This is a case where lithography is running up against the wall of physics, and physics is winning.

Related Stories
Why EUV Is So Difficult
One of the most complex technologies ever developed is getting closer to rollout. Here’s why it took so long, and why it still isn’t a sure thing.
7nm Lithography Choices
Four possible scenarios for patterning the next generation of chips.
Tech Talk: Double-Triple Patterning
What comes after double patterning and why you need to understand it.
EUV: Cost Killer Or Savior?
There’s no such thing as a simple cost decision with EUV at its current power level.



  • witeken

    But will 7nm (or 10nm for Intel) actually use quadruple patterning? One speculation is that since its features are about ~40nm minimum, Intel/TSMC might push double patterning to its theoretical limit of about ~40nm. So it’s not entirely clear to me what decision has been made by each company.

    • Ed Sperling

      That’s one of the discrepancies that makes it hard to figure out all of this stuff. Presumably Intel’s 10nm is the same as someone else’s 7nm using a 10nm BEOL. There are lots of unknowns about when EUV will be used, when it will be deployed for real, and for what metal layers. That will affect how seriously companies like Intel and TSMC approach multi-patterning. And then there is the cost issue. How many chipmakers are really going to be pushing to 7nm or 5nm, and when? And what kinds of volumes are they expecting to achieve to pay for that? It used to be that we could look ahead two or three nodes with clarity. Now it’s hard to figure out what’s going to happen at the next node–or even how to define the next node with some consistency.

    • Ed Sperling

      That’s one of the discrepancies that makes it hard to figure out all of this stuff. Intel’s claim is their 10nm is not the same as someone else’s 7nm. But alongside this, there are lots of unknowns about when EUV will be used, when it will be deployed for real, and for what metal layers. That will affect how seriously companies like Intel and TSMC approach multi-patterning. And then there is the cost issue. How many chipmakers are really going to be pushing to 7nm or 5nm, and when? And what kinds of volumes are they expecting to achieve to pay for that? It used to be that we could look ahead two or three nodes with clarity. Now it’s hard to figure out what’s going to happen at the next node–or even how to define the next node with consistency.

  • memister

    Isn’t quadruple patterning already being used for NAND and DRAM at design rules equivalent to 5/7nm? That should imply problems already resolved.

    • witeken

      Well, yes, but no, building a gazillion, nicely ordered NAND gates is a whole lot easier than full blown logic, so it is not comparable.

      • memister

        The NAND cells are SAQP, so the cost is not prohibitive, as sometimes hinted. Logic may not be so different if it’s already at SADP stage.

      • memister

        40 nm pitch SADP not too different from a set of parallel lines. k1=0.28.

      • memister

        The final quadruple patterning for logic may indeed not be the same as memory but perhaps any similarities can be exploited.

  • memister

    I have read some estimates that an EUV single exposure is currently more expensive than a standard immersion LELE double patterning and also more expensive than SADP self-aligned double patterning. These estimates make sense as these techniques are being used today for 14/16nm and 10nm production, respectively, instead of EUV. It is also known that the current limit of patterning is around 40 nm pitch as mentioned by witeken, and this uses SADP. However, to get a full node shrink from this point requires going to 28 nm pitch, and that will require LELE double patterning with EUV, i.e., two EUV exposures: http://www.euvlitho.com/2016/P61.pdf . Thus, it seems immersion quadruple patterning will be cheaper going forward, even though it has more sources of variation due to two double patterning steps being used together.

    • Mark LaPedus

      Hi memister. Here’s my 2 cents worth…..You are correct. SADP and/or SAQP are used for leading-edge
      DRAM and NAND. They work, but I believe these are more regular patterns. However, logic is slightly different—the patterns are somewhat irregular. Making the lines with SADP and/or SAQP are not the problem. But making the cuts with SADP/SAQP (or LELELELE) is tricky. It’s doable, but it isn’t easy at 7nm. Overlay, EPE and variability issues surface. For
      a good explanation of this, listen to Rick Gottscho’s presentation during Lam’s annual meeting. http://investor.lamresearch.com/events.cfm . Here’s the real
      question—What about 5nm? Do you need SAQP or SAOP for 5nm? Or EUV? Or both EUV and SAQP. Or magic? Answer: It’s still up in the air.

      • memister

        My understanding is that memory uses 2 or 3 masks per SADP/SAQP. But for logic, there will be fewer masks, i.e., cuts, if the spacer masks the dielectric between conducting features rather than the conducting features themselves.