Discontinuities involving lithography and complexity will result in significant changes starting this year.
Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We believe that this makes them think a little harder before making bold statements that they may feel foolish about later. If you want to check out how they did last year you can find the retrospectives here and here.
This year, the predictions are divided into the following segments: Markets, Semiconductors, Manufacturing and Design, and Tools and Flows. This segment holds those related to Semiconductors, manufacturing and design.
There are a lot of changes happening in the manufacturing area and a lot of attention is being placed on the foundries. These changes are causing ripples throughout the whole system. “Even though Moore’s Law makes everyone in the supply chain stay on their toes to keep up with the constant cycles of change, big discontinuities are rare,” says Aki Fujimura, CEO of D2S. “The industry tends to stick with what it knows. Like a big earthquake, after a few generations, incremental improvements on the status quo just can’t keep up any more. In semiconductor manufacturing, the big quake is coming soon. It might not be this year. It might be next. It might not be 7nm. It might be 5nm.”
Some of the discontinuities are not planned. Chi-Ping Hsu, senior vice president and chief strategy officer for EDA products and technologies at Cadence explains one such change. “With the 28nm process, foundry compatibility has become extremely difficult, but you could use the same masks and go to different foundries as a second source. At 20nm, there is Double Patterning, and at 16nm you add the finFET structure. While each of these processes uses the same manufacturing equipment, the recipe for how they do the process flow has started to diverge quite significantly. Everyone has their own special way for doing DFM, OPC and different layers. The complexity has increased quite significantly, and second-sourcing requires a complete re-implementation. The complexity is driving the foundries to be the technology owners today. In the past, design companies had a lot of process development know-how, and these companies would help the foundry define the process. That is not the case any longer.”
In fact we have seen the increasing necessity for foundries, IP companies and EDA companies to collaboratively work on getting new processes ready. “The infrastructure and the ecosystem to support the process have become very expensive,” continues Hsu. “There are so many more derivatives of a particular process to match specific market segment needs. This is a new challenge, and we find ourselves having to ask which out of the ten are we are really going to support. If you attempt to do them all, it becomes a very heavy-duty, high-cost development. Almost all physical IP and analog IP will have to be redesigned for each variation.”
There has long been a desire to improve some of the equipment used for manufacturing. “The push to be able to use EUV for the critical layers is around the corner for wafer manufacturing,” believes Fujimura. “Other alternative solutions such as nanoimprint lithography (NIL), directed self-assembly (DSA), and e-beam direct write, will see significant announcements in their progress on the long road toward adoption for high-volume manufacturing in 2016.”
Fujimura says that the eBeam Initiative’s annual survey reveals that the majority of the luminaries in the semiconductor manufacturing supply chain believe that multi-beam writing machines will be used in high-volume manufacturing for critical-layer masks by the end of 2018. “This discontinuity fully enables the manufacture of curvilinear shapes on masks, which allows complex or even curvilinear patterns to be used for inverse lithography technology (ILT) to get better process margins on the wafer for small shapes with either today’s 193i wafer lithography solutions or EUV. Complex shapes are needed to manufacture the guide patterns for DSA, even if the desired shape on the wafer is a set of circles for Through-Silicon Vias and contacts, for example.”
Materials are another area of change. “Wide bandgap gallium nitride (GaN) and silicon carbide (SiC) are seeing adoption in power devices for automotive applications,” says Amit Nanda, vice president of global marketing at Silvaco. “There is also some very interesting work in looking at reactor scale simulations to more tightly couple what equipment manufacturers optimize and its impact in the fab.”
The ecosystem continues to get their collective minds around finFETs. “As companies adopt finFETs, the productivity of their physical designers is going to take a big hit,” says Graham Etchells, marketing director of AMS at Synopsys. “The complexity of new rules, restrictions such as fin placement, higher parasitics, metal track requirements and the high impact of layout dependent effects all degrade designer productivity. Using traditional, manual custom design won’t cut it. When one device in the schematic can translate to hundreds of devices in the layout, you need an alternative approach.”
Etchells believes that constraint-driven, fully automated placement and routing is not the answer. “Putting in constraints to get what you want is tedious and time consuming, and you never get what you really want anyway. Assisted automation is what’s required. Using the expertise and experience of the layout engineer, along with some interactive ‘power tools’ for placement and routing, will be the most effective means of tackling finFETs in 2016 and beyond.”
FinFETs also are adding complexity to other parts of the process. “Advanced reliability of finFET technologies with thermal-aware electromigration (EM) are emerging as a critical need,” points out Norman Chang, vice president and senior product strategist at Ansys. “This is due to the large self-heat-induced Delta-T’s on devices, interaction between devices and wires, and also Joule heating-induced Delta-T’s on wires, including thermal coupling among wires. We specifically see mobile, server, and automotive markets driving this need.”
As dimensions get smaller, memories are always on the front lines. “Memory technology is seeing lots of development,” says Nanda. “Precise physical simulation of high aspect ratio etching for 3D NAND, STT Magnetoresistive RAM is getting interest to ensure high yielding manufacturing. Even at the very microscopic TCAD-level simulation, we are seeing abstraction and an interest in dealing with large structures. Advanced devices and processes require analyzing physics phenomena but often on larger structures. Improved parallelization and numerics are getting more R&D emphasis.”
Graham Bell, vice president of marketing for Real Intent provides the NAND process roadmap from TechInsight as a preview of what will happen in 2016 for technology development. “Samsung and Toshiba/SanDisk will introduce their 12(10) nm technology node for the memory marketplace. Micron/Intel Corp. and SK Hynix will be playing catch-up to reach Samsung and Toshiba/SanDisk in the 3D memory space. The introduction of their 32-level offerings will provide 192Gb parts in the marketplace.”
One area that is certainly heating up is packaging. “2016 will be a turning point for people to seriously look at product shipments in the 2.5D and 3D IC space,” says Hsu. “This is not limited to just communications and high-performance markets. When we talk about process node advancements, a lot of the focus is on digital applications. Analog has tended to lag behind in using the latest process technologies, as analog design may not benefit as much from smaller geometries of advanced process nodes. More people are thinking about separating RF/analog and digital onto different dies and then packaging them together to get the best of both worlds. For the first time, there are one or two applications where there is now talk about stacked die being cheaper when compared to a single integrated, monolithic die. This is a big change in cost structure, and in the past, the cost of multiple dies was always higher than a single die. Once the cost crossover happens, the adoption will be quite straightforward because the technology is already proven.”
Chang adds “we expect fan-out on wafer-level packaging (FO-WLP) type of process technology to be adopted in mass production for the mobile market, declaring 2016 as the breakthrough year for starting the 3D-IC era. This requires a whole new flow for power, reliability and signal Integrity verification due to multiple dies shared on a silicon substrate.”
Not all see disaggregation of functionality happening in 2016. “There will be increased integration of wireless IP into monolithic solutions, in particular Bluetooth Smart and other low bandwidth solutions,” says Ron Lowman, strategic marketing manager for IoT at Synopsys. “System-in-Package (SIP) solutions will no longer be cost or power competitive.” He also sees other areas in which there will be increased integration. “MEMS solutions will increasingly integrate processing cores and non-volatile memories. They will basically integrate the microcontroller into the solutions to add intelligence, reduce chip counts per design, simplify the supply chain, increase integration levels, and ultimately lower costs and power consumption.”
Indeed, the definition of the ‘system’ is rapidly changing. “Sustained growth will come from success expanding beyond design automation focused only on semiconductors,” says Brian Derrick, vice president of marketing for Mentor Graphics. “It will expand to incorporate the many domains that are already part of electronic systems design and beyond as technology becomes increasingly complex along multiple vectors. Some of the most interesting opportunities will come at the intersections of specific and historically separate domains. Where, for example, do the domains of hardware, software, mechanical, chemical, biological and RF/communications overlap with work being done in applied aesthetics and human-machine interaction? And what are the biggest systems integration and verification challenges when it comes to systems-within-systems, such as already increasingly complex automobiles interacting within other systems? In the future, these are the sort of questions design automation companies should be helping to answer.”
When talking about systems-of-systems, it is difficult not to think about the Internet of Things (IoT). “Chips produced for IoT applications will be more complex that many people expect,” says Adnan Hamid, chief executive officer of Breker Verification Systems. “Driven by the need for better security and multiple communications methods, processing power will need to be greater than what a low-end microcontroller can provide. In order to keep power consumption as low as possible, multi-CPU designs will be preferred over a single high-performance processor. This will continue the trend seen in 2015 where SoC designs contained multiple processors with cache coherency requirements, extending the trend into a lower tier of applications. This architecture will make IoT chips much harder to verify and will drive development teams to adopt the techniques already in use for more traditional SoC designs.”
All of these changes are putting increasing pressure on EDA vendors and designers as they now have to deal with many more issues than they did in the past. Nanda provides a few examples: “Besides continued interest in circuit level variation and power integrity analysis at advanced nodes, we are seeing interest in understanding the impact of MEOL parasitics on extracted RC values. Analysis of extracted RCs for foundation blocks such as SRAM, NAND using 3D field solvers is becoming more relevant.”
The last word today goes to Fujimura who says “2016 will be an exciting time. All these changes can’t happen in one year. But significant milestones are expected to be announced in 2016 for all lithography alternatives, and particularly in mask making.”