As semiconductor designs become more complex and unique, so do the packages around those chips.
The semiconductor package is changing. What was until very recently considered an afterthought is now becoming a key part of the design process at all major chipmakers, and a critical factor in the extension of Moore’s Law.
This is a sharp reversal of what was almost universally an afterthought in planar silicon design and manufacturing. Rarely was the package an integral part of the architecture, and key metrics more often than not were price and durability. After 28nm, though, and in many IoT applications, packaging is becoming a differentiator. It’s also something that has to be revisited at every step of the flow, from initial concept and design all the way through to manufacturing.
“There have always been three pillars in semiconductor engineering—lithography, transistor design and materials,” said Jim McGregor, principal analyst at Tirias Research. “But challenges on the lithography side are stressing Moore’s Law. As a result of that, packaging has emerged as a fourth pillar. We’re moving from millimeter squared to millimeter cubed. System-in-package is now critical for a lot of things, and we’re seeing this with architectures from Freescale, Intel, Marvell and others.”
McGregor noted this shift isn’t optional for some markets. It’s actually a requirement for certain form factors because of power budgets, thickness of the package and, in some cases, flexibility. It takes less energy to send signals across fewer wires if the distances are shorter and the interconnects are thicker. “There are a lot of materials involved in this, and there’s a lot of innovation going on at the process level. This will become a critical differentiator.”
Yole Développement, in a report issued this month, likewise flagged 2015 as a new era in electronics, and the entry point for advanced packaging into scaling and functionality roadmaps. The research house pointed to advanced packaging for cost reduction, performance boost and functional integration, and predicted it would account for 44% of all packaging services by 2020, or roughly $30 billion.
Yole’s report identified smartphones and tablets as the main market for advanced packaging, with servers, PCs, gaming platforms, TVs and set-top boxes as other applications that will take advantage of packaging, as well as wearables and other IoT devices.
Likewise, Richard Gottscho, executive vice president of global products at Lam Research, noted in a presentation to analysts in July that advanced packaging would represent a sizeable market going forward, boosting markets for everything from high-aspect ratio dielectric etch and atomic layer deposition to TSV etching.
This is all good news for the packaging industry, and commercial chips are being developed today using new packaging approaches ranging from fan-outs to 2.5D, with monolithic 3D on the horizon. But this isn’t yet a high-volume market, and there are no well-defined processes or history of what works best for which markets.
“There are too many package types and too many process flows,” said Tom Salmon, vice president of global member services and standards at SEMI. “The packaging houses are serious about cost, and to keep those costs down they’re going to need to get serious about standards. We’re looking at bringing in a technical committee for multi-die integration.”
One effect from all of this experimentation is that it’s becoming harder to distinguish between what’s a chip, what’s a board, and what’s a system. The boundaries for each of them is being stretched and tested as the entire semiconductor industry looks for the best options for the future and ways to streamline the development process.
“What we’re seeing now is a blurring of the lines between PCB and the package,” said Ian Dennison, senior group director for the custom IC and PCB group at Cadence. “In some cases, this could be little more than an open system in a package.”
There is no shortage of options to achieving a working design. There are even multiple ways to get there. Small companies can offload to packaging houses, which may range from OSATs to foundries. Many midsize and large companies are working out at least some of these options by themselves.
“There is a lot of innovation going on at the SoC and SiP level for packaging because of the IoT,” said Dennison. “So you can integrate MEMS sensors on a separate die and control the connectivity.”
What’s in the package
Packaging, at least for now, is as unique as the chips on or in them, and so are the approaches by packaging houses. This has added a great deal of confusion at the starting gate.
eSilicon, which is developing 2.5D for the networking and high-performance computing markets, is functioning as part expert, part pioneer in this new packaging paradigm.
“We’ve seen demand explode this year, driven by HBM (high-bandwidth memory),” said Bill Isaacson, director of ASIC marketing at eSilicon. “The big issues we’re dealing with are the interposer cost and concern about yield in the foreseeable future. We’ve done a number of test chips to analyze other technologies besides silicon, and today we can build with reasonable confidence a chip that will be manufacturable and will work.”
That chip can be packaged by a variety of companies, as well. Large OSATs have been developing deep nanometer expertise, including the purchase of some advanced semiconductor manufacturing equipment, over the past half-dozen to complement their packaging skills. At the same time, large foundries such as TSMC, GlobalFoundries, Samsung, SMIC and UMC have been adding advanced packaging expertise. And not to be left out, electronic manufacturing services providers such as Foxconn and Jabil, are extending their reach beyond PCBs. Each of those uses a different starting point.
“When it comes to the materials assembly process, that varies tremendously,” Isaacson said. “Each one is different, and there is not a lot of evidence existing about which way is better. Some processes are very different. So you may have three or four things in the package—an ASIC, HBM (high-bandwidth memory), interposer and package—but there are a lot of possible ways to put them together. There is a near infinite number of ways you can combine chips in a package. There also are challenges about what’s reusable.”
How chips are packaged together has a cascade effect on other areas of a design, too. Simple changes in the package can radically change the electrical or thermal characteristics of a packaged system.
“In the early analysis, you need to be thinking about the RTL power model where you design early power analysis,” said Vic Kulkarni, senior vice president and general manager of the RTL Power Business at Ansys. “You need to understand how the RTL, gate level, and package all come together. That includes high peak power and high di/dt frames (instant rate of current change), so you can estimate which ones can cause problems downstream. There is no physical layout at that point, but you still need to do early power grid planning. Then you can create a chip power model and connect the dots across various models and figure out how to extract and encapsulate.”
While this has been done for planar SoCs at the leading edge of design, it now needs to be done for all chips using advanced packaging. The tools exist to make this happen, but the expertise for using those tools is heavily weighted toward the front end of the design-through-manufacturing flow.
“This involves how early power grid impacts impedance, power noise, electromigration and on-chip ESD,” Kulkarni said. “We’re already dealing with this with 16nm finFETs, where there are very thin lines and very high switching currents. For those designs, on-chip electromigration is an important parameter, especially when you’re designing libraries. We now have to characterize what’s inside a cell. It used to stop at the boundary of the cell. Now you have to look at EM hotspots throughout the package, which requires more use of models.”
Materials and unusual combinations
To make all of this work better, companies are developing a raft of new materials for packages, ranging from organic interposers to complex polymers. This is making for some unusual combinations of companies working together, as well.
New materials are essential, particularly in monolithic 3D packages, to prevent cracking that has appeared when holes are drilled into strained silicon or the chips are thinned out to usable thicknesses. Monolithic 3D potentially could be the lowest-cost solution for high-volume applications if new polymers are proven to be commercially viable. In those cases, the question is how many holes can be drilled in a substrate for TSVs, how quickly, and how closely together.
Taiwan’s ASE and Japan’s TDK announced in May that they were setting up a joint venture called ASE Embedded Electronics. The stated goal is to manufacture embedded substrates, with initial plans to thin chips down to 50μm in a four-layer plastic substrate.
“We’re seeing a shift from chip scaling to system scaling,” said SEMI’s Salmon. “With that shift there are very few packages that are single-die packages. Some are homogeneous, meaning from one company, which is simpler. Some are heterogeneous, with means that if they don’t do co-design and collaboration at the system design level they’re going to run into problems. What’s also new is that people are using packaging to scale. The topic has really shifted from chip scaling to system scaling, and the semiconductor industry is not very good at that. The industry is used to working in silos. But they’re rapidly finding as they push more into the consumer world, that doesn’t work very well.”
The breadth of that challenge is enormous. “The responsibility that we as OSATs have is to be able to describe this in a simple way,” said William Chen, senior technical advisor at ASE Group. “Engineers like infinite possibilities. Our goal is to bring them one or two tried and true ideas. In most packages there is a sweet spot, and then there are other choices. You have to stay in the sweet spot.”
Packaging also varies greatly by market. A package that is proven in the automotive market, for example, will be different than in the consumer market.
“With SiP, we are still looking at how to talk to the final user,” Chen said. “You start with co-design and co-development of IP, and then you take it down to the system people. The challenge is to be able to take it to the system guys so they have a much shorter development time. Right now you hear a lot out of all of us as we’re learning how to walk the walk. We are in a transition state, and the discussion about SiP is in a very disruptive phase.”
Processor companies such as Intel and IBM and FPGA vendors such as Xilinx will follow Moore’s Law as long as it is feasible. At the present, 7nm is firm on the roadmap, while 5nm is still questionable. This isn’t surprising. The semiconductor industry has never had visibility beyond two process nodes.
But there’s also widespread agreement that it’s getting harder—more expensive and more time consuming—to move forward by just shrinking features. New ways of packaging are a different path for adding performance, power and area improvements, not to mention new features and capabilities. And ultimately they can provide huge cost benefits by limiting the size and complexity of the individual die in a package. While this has been talked about for years, the floodgate is now open and companies across the supply chain are developing solutions that will propel the semiconductor industry forward for the next couple decades.
But what are the winning processes, formulas and materials, and which companies are best positioned to take advantage of those changes? So far, there is no clear answer to any of those questions.