category: Test, Measurement and Analytics

category: Auto, Security & Edge AI

Development Of High Voltage General-Purpose Pin-Electronics
By Advantest - 06 Jul, 2021 - Comments: 0

Currently, there is a demand in Automated Test Equipment (ATE) to test both high-speed/low-voltage amplitude devices manufactured in advanced processes and low-speed / high-voltage amplitude devices manufactured in legacy processes by a pin-electronics equipment. However, it is difficult to achieve both the operating speed over than 1Gbps and the wide I/O range over than 10Vpp, due to the trade... » read more

Driving Toward Predictive Analytics With Dynamic Parametric Test
By Alan Hart - 06 Jul, 2021 - Comments: 0

The foundation of parametric test within semiconductor manufacturing is its usefulness in determining that wafers have been fabricated properly. Foundries use parametric test results to help verify that wafers can be delivered to a customer. For IDMs, the test determines whether the wafers can be sent on for sorting. Usually inserted into the semiconductor manufacturing flow during wafer fabric... » read more

IC Data Hot Potato: Who Owns And Manages It?
By SE Staff - 06 Jul, 2021 - Comments: 1

Modern inspection, metrology, and test equipment produces a flood of data during the manufacturing and testing of semiconductors. Now the question is what to do with all of that data. Image resolutions in inspection and metrology have been improving for some time to deal with increased density and smaller features, creating a downstream effect that has largely gone unmanaged. Higher resoluti... » read more

Advanced mm-Wave And Terahertz Measurements With Cascade Probe Stations
By FormFactor - 06 Jul, 2021 - Comments: 0

The strong market needs to embed multiple functionalities from different semiconductor processing technologies into a single system continue to drive demands for more advanced 3DIC packaging technologies. Dimensions of copper pillar micro-bumps are consistently reduced in every new technology node to facilitate the 3D stacking of multiple dies so that overall system performance can be improved.... » read more

3 Technologies That Will Challenge Test
By Ed Sperling - 08 Jun, 2021 - Comments: 0

As chips are deployed in more complex systems and with new technologies, it's not clear exactly what chipmakers and systems vendors will be testing. The standard tests for voltage, temperature and electrical throughput still will be needed, of course. But that won't be sufficient to ensure that sensor fusion, machine learning, or millimeter wave 5/6G will be functioning properly. Each of tho... » read more

Reliability Costs Becoming Harder To Track
By SE Staff - 08 Jun, 2021 - Comments: 0

Ensuring reliability in chips is becoming more complex and significantly more expensive, shifting left into the design cycle and right into the field. But those costs also are becoming more difficult to define and track, varying greatly from one design to the next based upon process node, package technology, market segment, and which fab or OSAT is used. As the number of options increases fo... » read more

Is There a Practical Test For Rowhammer Vulnerability?
By Bryon Moyer - 08 Jun, 2021 - Comments: 3

Rowhammer is proving to be a difficult DRAM issue to fix. While efforts continue to mitigate or eliminate the effect, no solid solution has yet made it to volume production. In addition, more aggressive process nodes are expected to exacerbate the problem. In the absence of a fix, then, testing may be one way to give DRAM manufacturers and users some way to segregate devices that are more su... » read more

Digging Much Deeper With Unit Retest
By Anne Meixner - 08 Jun, 2021 - Comments: 0

Keeping test costs flat in the face of product complexity continues to challenge both product and test engineers. Increased data collection at package-level test and the ability to respond to it in a never-before level of detail has prompted device makers and assembly and test houses to tighten up their retest processes. Test metrology, socket contamination, and mechanical alignment have alw... » read more

Expanded Material Metrology For Refined Etch Selectivities
By Anoop Somanchi - 08 Jun, 2021 - Comments: 0

Trends in advanced device fabrication require combined lithography-etching multi-patterning sequences and self-aligned multi-patterning to form devices’ finest features at subwavelength dimensions. As EUV lithography (13.5 nm) progresses to larger numerical apertures and new thin resists, new multipatterning sequences must be developed with mutually compatible resists and proximal layers t... » read more

Signal Connectivity Checks Are Not Just For Design-For-Test Teams
By Pawini Mahajan - 08 Jun, 2021 - Comments: 0

By Pawini Mahajan and Raja Koneru The complexity with system-on-chip (SoC) design continues to grow, creating greater complexity of the corresponding design-for-test (DFT) logic required for manufacturing tests. Design teams are challenged not only by high gate counts and the array of internally developed and third-party IP integrated into their designs: the need to achieve high-quality manu... » read more

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