Scalable manycore architecture; thermal management and packaging of power devices; neuromorphic processor; auto creation of HBM architecture; processor fuzzing; vertical GeSn nanowire MOSFETs; automated chiplet design; self-driving 360/3D visual perception; EUV lithography; new 2D non-VdW materials.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory | ETH Zurich and University of Bologna |
| Thermal management and packaging of wide and ultra-wide bandgap power devices: a review and perspective | Virginia Polytechnic Institute and State University, U.S. Naval Research Laboratory, and Univ Lyon, CNRS |
| Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design | imec and KU Leuven |
| Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages | Politecnico di Milano and TU Dresden |
| HyPFuzz: Formal-Assisted Processor Fuzzing | Texas A&M University and Technische Universität Darmstadt |
| Vertical GeSn nanowire MOSFETs for CMOS beyond beyond silicon | Peter Grünberg Institute 9, JARA, RWTH Aachen University, CEA, LETI, University of Grenoble Alpes, University of Leeds, and IHP |
| Automated Design of Chiplets | UC Berkeley and Peking University |
| NVAutoNet: Fast and Accurate 360∘ 3D Visual Perception For Self Driving | NVIDIA |
| Particle charging during pulsed EUV exposures with afterglow effect | ASML, ISTEQ B.V., and Eindhoven University of Technology |
| A New Group of 2D Non-van der Waals Materials with Ultra Low Exfoliation Energies | TU Dresden, HZDR, and Aalto University |
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