Next-gen 3D NAND depends on the performance and repeatability of cryogenic etching processes
Increased storage needs at the edge and in the cloud are fueling rising demand for higher-capacity flash memory across multiple applications.
Released every 12 to 18 months, 3D NAND scaling outpaces most other semiconductor devices in replacement rate and performance gains. With each new generation, NAND suppliers deliver 50% faster read/write speeds, 40% greater bit density, lower latency, and greater power efficiency.
3D flash manufacturers sustain this incredible pace by stacking and connecting memory cells through tiny, deep channels that become smaller and deeper with each new generation. A breakthrough technology, cryogenic etching can drill billions of channel holes up to 10 microns deep through an opening of just 100nm with near-vertical profiles. In an industry that values energy efficiency and sustainability, these innovative etching tools are designed to use half the energy of previous cryogenic solutions, while reducing carbon emissions by more than 80%.
For NAND etching processes, the key challenge is maintaining reasonable etch rates together with vertical profiles from the channel’s top to bottom. Modeling plays an increasingly important role in optimizing process recipes to ensure vertical profiles without CD variation, bowing, and hole shape distortion inside memory holes. AI is helping to optimize the profiles of these features even when only a small data set is available. The reason these memory profiles are so critical is that their uniformity is directly tied to NAND performance, measured as read/write speed and program/erase efficiency.
The top producers of 3D NAND chips include Samsung Electronics, Western Digital, Kioxa (Toshiba), SK hynix, and others. By stacking more but thinner alternating layers of silicon dioxide and silicon nitride (ON), they add 30% more word lines in each device generation. Then, deep reactive ion etch (DRIE) technology drills billions of high-aspect-ratio cylinders (with depth-to-width ratios exceeding 50:1) into the chip.
DRIE reactors preferentially direct ions vertically, enabling parallel structures for deep trench isolation, through-silicon vias, MEMS cavities, and other vertical constructs. In NAND flash, even the slightest atomic-scale deviations from the target profile of these features can degrade the device’s electrical properties, reducing yield and performance, and potentially compromising reliability.
The allowed profile deviation in a 100nm hole, 10 microns in depth, is only 10nm. “So if you think about 10-nanometer profile deviation as a function of the depth, this is less than 0.1% profile deviation, which is truly impressive,” said Tae Won Kim, corporate vice president of global etch products at Lam Research.
How 3D NAND scales
3D NAND chipmakers utilize three key methods to scale their devices (see figure 1). Flash cells can be placed closer together (x and y scaling), or stacked using vertical connections. Since the industry transitioned from 2D to 3D NAND, around 2014, flash manufacturers have mainly built in the vertical direction while also positioning the logic circuitry below the memory array to further reduce the footprint (called chip under array, or CUA). Chipmakers also are increasing the number of bits per cell without enlarging the area, going from single bits to 4 bits per cell (quadruple level cell) and beyond, which increases the number of voltage states.
Fig. 1: NAND scales by reducing cell pitch and size, stacking word lines and increasing the number of bits per cell. Source: Lam Research
How did we get here?
Competition is fierce among NAND chipmakers, which push for outstanding uniformity repeatability in every fabrication step. The part is the memory hole channel etch. Other important high-aspect-ratio etches for NAND include:
After the vertical channel etching process, the oxide and trapping layers and the polysilicon channel are deposited along the sidewalls of the holes. This arrangement is often referred to as the macaroni channel.
Fig. 2: Schematic of a 3D NAND gate-all-around architecture showing one vertical string of charge trap cells with oxide-nitride-oxide (ONO) gate dielectric, and a limited number of word lines. Source: imec
In most NAND products, the charge-trap cell built in vertical strings has replaced the floating gate (FG) transistor, built over the source/drain. While both devices operate similarly, the charge-trap cell resides in a nitride layer deposited in the gate oxide (between the source and drain), essentially a vertical MOSFET device with a silicon nitride trap layer inside.
Once the cell array is completed, chipmakers often fabricate a second tier or stack, which is later connected in a string. “But ensuring a consistent diameter string through this ~30µm-thick layer stack induces ever higher processing complexity and cost, challenging the tall stack deposition and high-aspect-ratio etch steps,” noted Sana Rachidi, senior integration researcher in the Memory Process Integration team at imec. [1]
While a multiple shorter-tier approach can reduce the burden on high-aspect-ratio etch tools, it also adds cost and complexity, especially because the multiple memory holes in one tier need to line up with the holes in the second tier, as they are later connected. There is a tradeoff between having shorter tiers that must line up and pushing the performance of etching to carve out deeper regions in the ON stack.
For now, NAND suppliers are packing as many memory cells as possible into a single tier, then building the second tier. “Another trend is to optimize the peripheral CMOS circuitry on a different wafer and attach it to the memory array stack using hybrid bonding techniques,” Rachidi said. “To control the growing processing costs, an additional scaling is pursued in the vertical direction, referred to as z-pitch scaling.”
Why cryogenics?
In traditional RIE processes, the etch rate drops off as it removes more and more material inside tiny holes. Sometime in the 2010s, etch manufacturers began exploring low-temperature processing (0°C to -30°C) to see if the combination of cryogenics and alternative chemistry could accelerate the throughput of RIE systems while enhancing the vertical profiles.
By keeping the wafers cold, energetic fluorine and oxygen ions do the heavy lifting of removing the oxide-nitride layer and associated debris. “The lower temperatures suppress unwanted sidewall etch while enhancing ion mobility and bombardment,” said Lam Research’s Kim. The ultra-low temperature is achieved by using chillers on the etch platform and helium cooling of the wafer.
Chemically, the higher etch rate results from these increases in surface diffusion and physisorption of neutral species. Importantly, the process engineer needs to control the formation of polymers at the top of the hole, which can stop the ion flux from reaching the feature bottom. “Hole profile is controlled through the precise management of wafer temperature and gas chemistry, which exploits the temperature-dependent shift from chemisorption to physisorption of neutral species on the etch sidewalls,” Kim explained.
The necessary etch depth keeps increasing. “For the future generations with over 400 layers, a minimum of 8µm/tier depth memory channel hole etching is required in order to sustain current 2-tier stacks,” estimated Yoshihide Kihara and colleagues at TEL. [2]
Alternative chemistry enables both faster etch rates and hole depth while reducing carbon footprint. “By using HF gas for etching, the partial pressure of conventional CF gas can be greatly reduced, thus carbon footprint from greenhouse gases can be reduced by 84% compared to the first-generation cryogenic process,” TEL added. The company also found that small amounts of a phosphorus-containing gas (PF3) acts as catalyst to promote the reaction between HF and SiO2, increasing etch rates at lower temperature operation.
The need for cryogenic etching technology is already clear. Kim notes that Lam Research already has 1,000 chambers installed in production fabs for 3D NAND applications.
RIE is possible using two types of reactors — capacitively coupled plasma and inductively coupled plasma systems. Generally, ICP is more common because its two electrodes allow independent control of ion energy and ion density, while RF bias power accelerates active species into the hole.
There are several providers of RIE tooling, including Applied Materials, Plasma-Therm, Oxford Instruments and Sentech Instruments, but Lam Research and TEL are the dominant players in cryogenic etching for high-volume manufacturing. TEL introduced its first cryogenic etcher in 2023, while Lam Research introduced its third-generation cryoetcher in July 2024. Lam Research’s Kim noted how the three generations of reactors used three different chemistries. (Lam did not disclose the gas species currently being used.)
Another key ingredient to successful etching is the lithography and etch mask used to form the holes and slits. Chipmakers use thick amorphous carbon hard masks (deposited by CVD) with spin-on glass and photoresist on top to first pattern the hard mask. That thick mask protects the ON/ON/ON regions that should remain during etch.
Lam Research also employs plasma pulses to switch between etch mode and passivation mode. Byproducts of the etch process are important because they passivate the sidewall, preventing feature bowing. Already approaching 70:1 aspect ratio for the vertical channel etch, a transition to 100:1 aspect ratio will prove even more challenging to control.
Profile control, AI and etch recipes
Modeling is playing an increasingly critical role in improving fabrication results. When it comes to developing an etch recipe for optimal vertical channel etching in NAND, it’s instructive to note there are more than 30 tunable etch parameters, including temperature, gas flow rates, power, process time, and others.
Engineers from Macronix, led by Cheng-En Tsai, revealed an AI-based method for optimizing as-etched profiles in a vertical channel (VC) structure to minimize shape deformation in the VC profile. [3] Different from many AI-assisted modeling calculations that are built using large, diverse data sets, the Macronix group used data from 25 processed wafers (including wafer centers, middle, and edges) to optimize etching recipes for reduced CD variation. This approach reduces the cost and time associated with recipe development.
“One of the key challenges in the semiconductor industry is minimizing wafer consumption right from the outset of recipe development, as this is crucial for both cost efficiency and accelerating product development timelines,” Tsai and colleagues reported. The AI program was able to optimize 33 etching parameters to reduce variation in top CD, bow CD (widest point), CD distortion, and CD striation levels.
The core strategy behind Macronix’s AI-assisted tuning method is to fine-tune a pretrained transformer model based on a comprehensive data set. The fine-tuning process applies a machine learning algorithm to a small dataset from actual wafers and DOE splits. “The resulting VC profile is obtained by inputting the predicted etching parameters into the model, allowing the system to simulate and predict the VC structure with high accuracy,” said the Macronix team, highlighting the role of domain knowledge. “To improve the accuracy of the model’s predictions, certain predetermined parameters were set with specific constraints, based on expert knowledge in the field. This step was crucial for refining the model’s output and ensuring that the predictions were aligned with realistic and feasible etching conditions.”
Using TEM slope cut measurements taken at more than 10 depths in the VCs, critical dimension (CD) variations were recorded, and the ML determined optimized values for the 33 etch parameters. “By enabling the creation of highly accurate etching profiles, this method not only improves the quality of the etched structures, but also contributes to significant cost savings in the semiconductor industry. Through advanced optimization techniques, the AI-assisted tuning method ensures the resulting VC architecture exhibits exceptional performance in minimizing shape deformation and maintaining tight control over CDs.”
Most importantly, the new process recipe reduced feature distortion, which directly correlates with NAND performance and reliability. “In the presence of a poorly distorted VC shape, as seen in the initial process, the abrupt threshold voltage is evident, indicating performance instability during 3D NAND programming.” The AI-assisted etching process completely eliminated this threshold-voltage behavior, resulting in predictable, optimized device behavior.
Future scaling in peril?
To continue adding more ON layers each generation, it makes sense to reduce the z-pitch between word lines, which stands at approximately 40nm in existing devices. However, imec researchers caution that as NAND manufacturers continue to scale while using existing materials, two physical problems arise — lateral charge migration and cell-to-cell interference.
Charge migration and signal interference can reduce threshold voltage, enhance sub-threshold swing, decrease data retention, and increase the program/erase voltages. “When further reducing the thickness of the word-line layer, the gate length of the charge trap transistor shrinks accordingly. As a result, the gate increasingly loses control over the channel, facilitating electrostatic coupling between adjacent cells. In addition to cell-to-cell interference, the shrinking of the memory cells in the vertical direction leads to lateral charge migration (or vertical charge loss). Charges trapped inside the SiN layer tend to migrate through the vertical SiN layer, compromising the retention,” said the imec researchers.
One process change that would suppress cell-cell interference involves replacing the oxide dielectric with low-k air gaps between the word lines. In fact, air gaps were previously used for this purpose in 2D NAND devices. However, introducing air gaps in a vertical structure is much more challenging than in a planar structure.
Imec recently devised a reproducible air gap scheme that recesses the inter-gate oxide layers prior to depositing the ONO stack. [4] “The airgaps are introduced self-aligned to the word-line, allowing their positioning to be precisely controlled and providing a scalable solution.”
This and other schemes will be pursued by researchers and manufacturers to continue 3D NAND scaling.
Conclusion
Cryogenic etching is an essential development in RIE processes that enables the formation of extremely deep and thin cavities for vertical contact, slits, staircase contacts, and peripheral contacts in 3D NAND devices. Chipmakers are optimizing more than 30 etch parameters to ensure vertical profiles with low variation in CDs from feature top to bottom.
As this extremely challenging technology is extended, process simulation and AI assistance can play a significant role in recipe optimization without needing to run hundreds of development wafers. That saves costs and reduces time-to-market. As a result, the industry is likely to rely more heavily on virtual fabrication for these and other essential fabrication steps.
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