tag: imec

New Transistor Structures At 3nm/2nm
By Mark LaPedus - 25 Jan, 2021 - Comments: 12

Several foundries continue to develop new processes based on next-generation gate-all-around transistors, including more advanced high-mobility versions, but bringing these technologies into production is going to be difficult and expensive. Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s finFET transistors to new gate-all-around field-effect trans... » read more

Imec’s Plan For Continued Scaling
By Paul McLellan - 14 Jan, 2021 - Comments: 0

At IEDM in December, the opening keynote (technically "Plenary 1") was by Sri Samevadam of Imec. His presentation was titled "Towards Atomic Channels and Deconstructed Chips." He presented Imec's view of the future of semiconductors going forward, both Moore's Law (scaling) and More than Moore (advanced packaging and multiple die). It is always interesting to hear Imec's view of the world sinc... » read more

The Darker Side Of Hybrid Bonding
By Katherine Derbyshire - 17 Dec, 2020 - Comments: 2

With semiconductors, it's often things everyone takes for granted that cause the biggest headaches, and that problem is compounded when something fundamental changes — such as bonding two chips together using a process aimed at maximizing performance. Case in point: CMP for backend of the line metallization in hybrid bonding. While this is a mature process, it doesn't easily translate for ... » read more

AI And High-NA EUV At 3/2/1nm
By Mark LaPedus - 16 Dec, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

Manufacturing Bits: Nov. 25
By Mark LaPedus - 25 Nov, 2020 - Comments: 0

Lidar-on-a-chip At the upcoming IEEE International Electron Devices Meeting (IEDM), Samsung will present a paper on the industry’s first single-chip lidar beam scanner. (Go to this link and then look for paper 7.2, “Single-Chip Beam Scanner with Integrated Light Source for Real-Time Light Detection and Ranging,” J. Lee et al, Samsung.) Lidar, or light imaging, detection, and ranging, ... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 20 Nov, 2020 - Comments: 0

Fab tools PDF Solutions has entered into a definitive agreement to acquire Cimetrix. Under the terms, PDF will pay a cash amount of $35.0 million, net of cash on Cimetrix’s balance sheet as of closing, and subject to other closing adjustments. With the move, PDF will expand into new markets. Cimetrix is a provider of equipment connectivity products for smart manufacturing and Industry 4.0... » read more

EUV Challenges And Unknowns At 3nm and Below
By Mark LaPedus - 19 Nov, 2020 - Comments: 1

The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up. In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV pro... » read more

Improving EUV Underlayer Coating Defectivity Using Point-Of-Use Filtration
By Brewer Science - 18 Nov, 2020 - Comments: 0

Authors: Aiwen Wu (Entegris, Inc. — United States), Hareen Bayana (Entegris GmbH — Germany), Philippe Foubert (imec — Belgium), Andrea Chacko and Douglas Guererro (Brewer Science, Inc. — United States). This paper describes efforts to leverage different filtration parameters, including retention ratings and membrane materials, to understand their impact on EUV underlayer coating defe... » read more

Challenges Linger For EUV
By Mark LaPedus - 11 Nov, 2020 - Comments: 2

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

Manufacturing Bits: Oct. 12
By Mark LaPedus - 12 Oct, 2020 - Comments: 1

MoSi2 pellicles for EUV Hanyang University has presented a paper that describes a novel molybdenum disilicide (MoSi2) pellicle membrane for use in extreme ultraviolet (EUV) lithography. With a 28nm thickness, a MoSi2 membrane has demonstrated a 89.33% transmittance for EUV lithography. The pellicle technology is still in R&D. MoSi2, which is a silicide of molybdenum, is a refractory cer... » read more

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