tag: Lam Research

Week In Review: Manufacturing, Test
By Mark LaPedus - 27 Nov, 2020 - Comments: 0

Market research VLSI Research has raised its forecast for semiconductors and fab equipment in 2020. In its previous forecast, VLSI Research projected that the equipment market would reach $84.8 billion in 2020, up 10.1% over 2019. Now, in its latest forecast (See page 2), the equipment market is projected to hit $89.8 billion in 2020, up 16.6%. “The equipment business is booming,” said ... » read more

Accelerating Dry Etch Processes During Feature Dependent Etch
By Timothy Yang - 23 Nov, 2020 - Comments: 0

In dry etching, the trajectory of accelerated ions is non-uniform and non-vertical, due to collisions with gas molecules and other random thermal effects (figure 1). This has an impact on etch results, since the etch rate at any point on the wafer will vary depending on the solid angle visible to the bulk chamber and the ion flux for that angular range. These non-uniform and feature dependent e... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 20 Nov, 2020 - Comments: 0

Fab tools PDF Solutions has entered into a definitive agreement to acquire Cimetrix. Under the terms, PDF will pay a cash amount of $35.0 million, net of cash on Cimetrix’s balance sheet as of closing, and subject to other closing adjustments. With the move, PDF will expand into new markets. Cimetrix is a provider of equipment connectivity products for smart manufacturing and Industry 4.0... » read more

EUV Challenges And Unknowns At 3nm and Below
By Mark LaPedus - 19 Nov, 2020 - Comments: 1

The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up. In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV pro... » read more

From FinFETs To Gate-All-Around
By Nerissa Draeger - 19 Nov, 2020 - Comments: 0

When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As compared to prior planar transistors, the fin, contacted on three sides by the gate, provides much better control of the channel formed within the fin. But, finFETs are already reaching the end of their utility as... » read more

A Study Of Wiggling AA Modeling And Its Impact On Device Performance In Advanced DRAM
By Coventor - 18 Nov, 2020 - Comments: 0

In this paper, a wiggling active area (fin) in an advanced 1x DRAM process was analyzed and modeled using the pattern-dependent etch simulation capabilities of the SEMulator3D semiconductor modeling software. Nonuniformity in sidewall passivation caused by hard mask pattern density loading was identified as the root cause of the wiggling profile. The calibrated model mimicked these phenomena, g... » read more

FinFETs Give Way To Gate-All-Around
By Lam Research - 18 Nov, 2020 - Comments: 0

When they were first commercialized at the 22 nm node, finFETs represented a revolutionary change to the way we build transistors, the tiny switches in the “brains” of a chip. As compared to prior planar transistors, the fin, contacted on three sides by the gate, provides much better control of the channel formed within the fin. But, finFETs are already reaching the end of their utility as... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 06 Nov, 2020 - Comments: 0

Chipmakers Earlier this year, the semiconductor industry saw little merger and acquisition activity. More recently, though, there has been a flurry of deals. In July, ADI moved to acquire Maxim. Then, Nvidia announced plans to acquire Arm for $40 billion, followed by AMD’s proposed move to buy Xilinx for $35 billion. Not to be outdone, Marvell has announced plans to buy Inphi. Companies a... » read more

Micro Loading And Its Impact On Device Performance
By Qingpeng Wang - 02 Nov, 2020 - Comments: 0

In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1]. With transistor sizes approaching the lower limits of physical achievability, manufacturing variability and micro loading effects are becoming increasingly critical DRAM performance (and yield) limiters. The transistor’s AA (active area) dimension and profile... » read more

Blog Review: Oct. 28
By Jesse Allen - 28 Oct, 2020 - Comments: 0

Synopsys' Jacob Wilson provides some tips for how to prepare for the upcoming ISO SAE 21434 cybersecurity standard for road vehicles, starting with a security plan and understanding of risk levels. Cadence's Paul McLellan checks out Arm's first face-to-face wafer-bonded design, why it might be desirable, and some important aspects of how the proof-of-concept was developed. In a video, Men... » read more

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