tag: Mentor

Blog Review: Feb. 4
By Jesse Allen - 04 Feb, 2026 - Comments: 0

Siemens' Tova Levy examines thermal management in 3D-IC, including why heat behaves differently in vertical stacks and how to analyze and manage thermal risk earlier and more predictably to ensure a design can meet performance, reliability, and time-to-market targets. Cadence's Reela Samuel finds that known-good-die strategies, standardized die-to-die test access, and vertical reliability mo... » read more

Chiplet Fundamentals For Engineers: eBook
By Bryon Moyer - 02 Feb, 2026 - Comments: 1

Multi-die assemblies are the next phase of Moore's Law, scaling up and out  to improve performance and add flexibility into designs. By decomposing SoCs into building blocks, yield improves for the individual dies and overall performance increases because a chip is no longer bound by reticle limits. But this is much harder than it sounds. Chiplets don't just snap together like LEGOs, and so... » read more

Chip Industry Week In Review
By The SE Staff - 30 Jan, 2026 - Comments: 0

Big deals and fundings Teradyne and MultiLane are forming a joint venture, MultiLane Test Products (MLTP), to accelerate the development of test solutions for high speed data connections.  Teradyne will be the majority owner. Ricursive Intelligence raised $300M Series A for AI-driven IC design. IonQ plans to acquire SkyWater for ~$1.8B, creating a "vertically integrated full-stack q... » read more

Opening The Door To STCO: Hierarchical Device Planning
By Todd Burkholder - 29 Jan, 2026 - Comments: 0

By Todd Burkholder and Per Viklund The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high-performance market segments, such as AI, hyperscalers, high-performance computing, cloud data centers, neural processors, and even autonomous vehicles. This increased design complexity has led to an explosion in device complexity and pin counts. It... » read more

Does Your RISC-V Core Meet The Standard?
By Brian Bailey - 29 Jan, 2026 - Comments: 0

Key Takeaways Architectural conformance and implementation verification are necessary but different for RISC-V designs, yet few verification engineers have experience on the conformance side. While RISC-V enables flexibility, there is a potential for ecosystem fragmentation. It is mathematically impossible to test every instruction combination, so engineers are moving beyond just "bl... » read more

Multi-Die Assemblies Require More Detailed Test Plan Earlier
By Ann Mutschler - 29 Jan, 2026 - Comments: 0

Key Takeaways Design for test takes on new urgency in complex multi-die assemblies, where it can be used to minimize downstream errors and the cost of fixing them. DFT needs to be increasingly detailed due to more connections and the inability to access some components. DFT strategies need to be developed earlier and may require multiple testing approaches. Multi-die assembl... » read more

AI’s Impact On Engineering Jobs May Be Different Than Expected
By Liz Allan - 29 Jan, 2026 - Comments: 0

Key Takeaways: AI is expected to eliminate many repetitive, entry-level tasks, but that may allow engineering students trained on the latest tools to start in more senior positions. AI is a force multiplier. It can accelerate the learning curve for junior engineers. While AI is very good at solving multi-dimensional problems, domain expertise, critical thinking, and sanity checks wil... » read more

Blog Review: Jan. 28
By Jesse Allen - 28 Jan, 2026 - Comments: 0

Synopsys' Dana Neustadter and Vincent van der Leest argue that a hardware-based approach to security is required to fully address the risks introduced by modern AI architectures and the distributed workloads they support. Siemens EDA's Tova Levy examines multiphysics challenges in 3D-IC designs and outlines three design imperatives to identify risks earlier and support PPA, reliability, and ... » read more

New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity
By Siemens EDA - 28 Jan, 2026 - Comments: 0

The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high performance compute segemnts such as AI, Hyperscalers, Cloud datacenters, Neural processors and even autonomous vehicles. With the quantity of chiplets commonly exceeding double-digit numbers. Add to that the increasing usage of high-speed, low power and low latency high-bandwidth-memory ... » read more

Software-Defined Systems
By Ed Sperling - 26 Jan, 2026 - Comments: 0

Using high-level software languages to define semiconductors is faster, easier, and allows for more changes long before the RTL stage. This is especially useful for chiplets and embedded accelerators, which are narrower in scope and more targeted at different workloads and specific domains. But there are some caveats for engineers working in this space. Russell Klein, program director for Sieme... » read more

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