What’s Important For IoT—Power, Performance Or Integration?

Experts at the table, part 1: Different approaches are being considered for reducing power across a wide range of devices and applications, but pricing is still a challenge.


Semiconductor Engineering sat down with Steve Hardin, director of product development for AT&T’s IoT Solutions Group; Wayne Dai, CEO of VeriSilicon; John Koeter, vice president of the Solutions Group at Synopsys; and Rajeev Rajan, vice president for IoT at GlobalFoundries. What follows are excerpts of that conversation.

SE: One of the major issues everyone talks about when it comes to the IoT is power. How do we get the power down? Is it design, materials, or a rethinking of the architecture?

Hardin: One of the things we’re working on with all of our partners are a couple of technologies that don’t get used in wireless networks. One is called DRX (discontinuous reception), and another is called power-save mode. These are new developments that essentially allow even existing technologies to adapt to these solutions. IoT devices aren’t like smart phones where you want to get alerts on your e-mail as soon as it comes in. The network will be aware of these devices and know that they’re going to be asleep for longer periods of time, so it does not de-register them from the network. We’re going to be able to see that and take some of the current technology that exists. Once you put them in deep sleep modes, it won’t be uncommon to have them last 10 years on a battery. But at 10 years, the battery technology itself becomes challenging.

Rajan: One of the most important things about power is to realize what the device is going to do. If you have applications that need sustained power, usually they have a low operating requirement. Then they do burst processing, and then they come back down. If you can manage the interplay between power, the current requirement, and the kind of application being run, you can get a lot more juice out of the system. Technologies like FD-SOI speak exactly to that. There is power on one side, and leakage management on the other. If you can do the right tradeoff, it’s a good direction to go in. With the coming of 5G, we need to not just be thinking of a thing by itself. It’s more about how does one thing talk to another thing? It has to be able to manage not just its own power, but it has to manage communication with the other thing so that thing also manages its power.

Koeter: There are some very interesting ways to address the power issues involving design tools and design flows. There is a relatively new standard called UPF 3.0 for analyzing the architecture. At a system level and a chip level, you can model your chip using UPF 3.0 to get the best possible architecture. People use that typically in conjunction with real-world software to look at the power that is burning and how to minimize that. In the implementation flow there are things like dynamic voltage and frequency scaling, adjusting the clock frequency depending on the load on the chip. And then there are power islands and voltage islands. The fabs have been putting a tremendous amount of effort into driving the processes down from a voltage perspective. At 40nm they are running at 0.8 volts. That’s a very important number because it’s the voltage of a single AA battery at the end of its life. If you can have a fab process that runs at 0.8 volts at 40 or 50nm, that’s important. At finFET nodes, we’re hearing things south of 0.5 volts. That’s a significant way to manage power. And then if you look into the future, there are some interesting developments in energy harvesting, like capturing the energy when you’re breathing. Right now there is no efficient way to capture that, but someday they will. And on a highway, there is piezoelectric compression of the cement. Cities are starting to put capacitors along the side of the road and take the energy harvested at rush hour to power street lamps. It’s not very practical yet, but it is interesting. And the last example involves forest fires, which cause billions of dollars of damage. There is research going on where if you string a nail hammered into a tree and put the other end down into the ground, that generates a trickle current. There are people actively trying to do these mesh sensors out in the middle of nowhere powered by trees.

Dai: When we look at power, we think of the battery. But in other cases, it’s the heat envelope. With automotive and ADAS, sometimes it’s the heat that’s the problem. You have limits of how much heat it can generate.

SE: Where do standards fit in?

Hardin: A lot of wireless technology has been driven by a completely different segment. There had not been attention paid for this particular use case. That now has the focus of folks in standards committees. Now we need to get the volume to develop silicon just for these use cases. Because they don’t sell at the same premium of a cell phone, it has to be in numbers that exceed that. Any technology that improves power and helps drive volume will be helpful.

SE: We’ve heard that 55nm is the mainstream IoT process, but the reality is the IoT includes everything from sensors to servers in a data center.

Rajan: It’s a little bit of all of those. It’s not just which technology is the right one. From a commercial path standpoint, it’s which company is willing to adopt which technology. A few years ago, IoT was slated to be here by now. Now there are reports that IoT is slowing down. There were reports that 40nm was going to be a longer-lived node. Now there are reports that 40 and 28 are going to be longer-lived nodes because the adoption curve has slowed. Add to that the cost. If we are really looking for broader adoption, the cost points have to come down for the mass market. IoT was a broad horizontal platform. Now it is being viewed as a series of vertical implementations. It’s a combination of lack of standardization and fragmentation that’s driving the market. Over time, as the right forces gel together to bring the key parameters to drive adoption, standards will come in on top of that.

Koeter: We’re always tracking our presales opportunities for physical IP. Right now, we’re tracking about 150 designs in hard IP that are process-specific. About 60% of that is either 40 or 55nm, and 20% is at 28nm and below. Then there are a bunch of other technologies across the board in things like smart sensors.

Dai: Some people don’t move beyond 55nm because of leakage. Both finFET and FD-SOI are fully depleted. One is 3D, one is 2D. We believe both will co-exist. But we are really looking to design for FD-SOI, not just to port to there. You can use finFETs, but FD-SOI is easier. There is body biasing, which is very unique to FD-SOI. FinFETs cannot do that. Also, you may not need to sign off on the worst case. So when you look at area, cost, and include body biasing, you could have lots of advantages. I’ve also seen 0.6 volts and below. So you have lots of advantages. We also tape out using 14nm finFETs. We work with all the foundries, and we work with every 28nm, including high-k/metal gate. Sometimes people say a finFET is not justified. We find people need a lot of options.

Rajan: FD-SOI brings the best of the PPAC to bear. We have a low/medium/high distinction, and 22FD-SOI has the ability to be elastic across these capabilities. With 700MHz, that caters to the low-end/middle of the market. With 1GHz and above, that can cater to the high end of the market, too. That is also a very good technology. Every PowerPoint presentation needs to become an Excel spreadsheet for the finance guys. It comes down to price, performance, cost, as well as capabilities and performance levels. When we get to the point where we allow those technologies to be promulgated, that’s when we’ll see everyone crossing the chasm. From our standpoint, we enable all of those areas and help the customer to make the right choice.

Koeter: What’s interesting about the different process nodes is the level of integration you can achieve. Normally you think the most advanced process nodes have the highest level of integration, and that’s true from a gate count perspective. But with 55 and 40nm, you have eFlash processes, you have RF processes that are very key for wearables. That’s a high level of integration, and it’s one of the reasons people are staying at those nodes. If you go to FD-SOI or finFET, you get the balance of the power versus the performance. As you go down you get a roll-off in performance, and finFET is one of the ways to lower the voltage while still maintaining a certain level of performance.

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