category: Test, Measurement and Analytics

category: Auto, Security & Edge AI

Chip Monitoring And Test Collaborate
By Bryon Moyer - 11 May, 2021 - Comments: 0

As on-chip monitoring becomes more prevalent in complex advanced-node ICs, it’s easy to question whether or not it conflicts with conventional silicon testing. It might even supplant such testing in the future. Or alternatively, they could interact, with each supporting the other. “On-chip monitors provide fine-grained observability into effects and issues that are otherwise difficult or... » read more

Testing AiP Modules In High-Volume Production
By Jose Moreira - 11 May, 2021 - Comments: 0

Far-field and radiating near-field are two options for high-volume over-the-air (OTA) testing of antenna-in-package (AiP) modules with automated test equipment (ATE) [1]. In this article, we define an AiP device under test (DUT) and examine the measurement results from both methods. Creating an AiP evaluation vehicle Proper evaluation of an ATE OTA measurement setup requires an AiP module. Us... » read more

Testing Analog Circuits Becoming More Difficult
By SE Staff - 11 May, 2021 - Comments: 1

Foundries and packaging houses are wrestling how to control heat in the testing phase, particularly as devices continue to shrink and as thermally sensitive analog circuits are added into SoCs and advanced packages to support everything from RF to AI. The overriding problem is that heat can damage chips or devices under test. That's certainly true for digital chips developed at advanced node... » read more

Chasing Test Escapes In IC Manufacturing
By Anne Meixner - 11 May, 2021 - Comments: 0

The number of bad chips that slip through testing and end up in the field can be significantly reduced before those devices ever leave the fab, but the cost of developing the necessary tests and analyzing the data has sharply limited adoption. Determining an acceptable test escape metric for an IC is essential to improving the yield-to-quality ratio in chip manufacturing, but what exactly is... » read more

Cryostats Enable Astrophysics Research
By Paul Owen - 11 May, 2021 - Comments: 0

Imagine designing and building two prototype HPD cryostats for the Submillimeter Array on Maunakea in Hawaii. The SMA is a collaborative project between the Smithsonian Astrophysical Observatory (SAO, a member of the Center for Astrophysics | Harvard & Smithsonian) and the Academia Sinica Institute of Astronomy and Astrophysics. The SMA consists of eight radio telescopes operating fro... » read more

Acoustic Metrology for Fine Pitch Microbumps in 3D IC
By Onto Innovation - 11 May, 2021 - Comments: 0

The continuing shift to 3D integration requires formation of electrical interconnects between multiple vertically stacked Si devices to enable high speed, high bandwidth connections. Microbumps and through silicon vias (TSVs) enable the high-density interconnects for die-to-die and die-to-wafer stacking for different applications. In this paper, we present acoustic metrology techniques for the ... » read more

FPGA Prototyping: Supersizing Scale And Performance
By Synopsys - 11 May, 2021 - Comments: 0

Given the cost of re-spinning a system-on-chip (SoC), semiconductor companies have always looked for ways to verify and validate the SoC before tape-out. Prototyping using field programmable gate arrays (FPGAs) became a key methodology as part of this pre-silicon verification and validation effort. Click here to read more. » read more

A Novel Memory Test System With An Electromagnet For STT-MRAM Testing
By Advantest - 11 May, 2021 - Comments: 0

We have successfully developed, for the first time, a new memory test system for STT-MRAM at wafer-level where an electromagnet is combined with a memory test system and a 300 mm wafer prober. In the developed memory test system, an out-of-plane magnetic field up to ±800 mT can be applied on 10 x 10 mm2 in the 300 mm wafer with distribution of less than 2.5%. We demonstrated that the electroma... » read more

Debug And Traceability Of MCMs And Chiplets In The Manufacturing Test Process
By Guy Cortez - 16 Apr, 2021 - Comments: 0

Single die packages and products have been the norm for decades. Moreover, so has multi-chip modules (MCMs) or system in package (SiP) for quite some time. Understandably, with ASICs and SoCs becoming larger while silicon geometries continue to get smaller, there is an opportunity to combine even more functionality into a smaller form factor for the end product. Hence, new advancements in desig... » read more

AI In Inspection, Metrology, And Test
By SE Staff - 06 Apr, 2021 - Comments: 0

AI/ML is creeping into multiple processes within the fab and packaging houses, although not necessarily for the purpose it was originally intended. The chip industry is just beginning to learn where AI makes sense and where it doesn't. In general, AI works best as a tool in the hands of someone with deep domain expertise. AI can do certain things well, particularly when it comes to pattern m... » read more

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