category: System-Level Design

category: Auto, Security & Edge AI

Understanding The Differences Between Oscilloscopes And Digitizers For Wideband Signal Acquisitions
By Keysight - 28 Feb, 2024 - Comments: 0

Most of us remember the first time we used an oscilloscope. With one look at the large display, we could tell what was happening to our waveforms. From the earliest days, oscilloscopes have been a primary tool for quick visualization of time-variant waveforms, and over the years, they’ve become a core instrument on the bench. Wideband digitizers are related to modern oscilloscopes since both ... » read more

3D Connection Artifacts In PDN Measurements
By Cadence - 28 Feb, 2024 - Comments: 0

Authors: Ethan Koether, Amazon; Kristoffer Skytte, John Phillips, Shirin Farrahi, Cadence; Joseph Hartman, Oracle; Sammy Hindi, Ampere Computing Inc.; Mario Rotigni, STMicroelectronics; Gustavo Blando, Istvan Novak, Samtec From a simulation stand-point, we have covered several important topics that users must consider in detail to get accurate low frequency simulation results. We investigate... » read more

Remote Droop Detection And Response Use Case
By Movellus - 28 Feb, 2024 - Comments: 0

While sea of processor architectures feature a stamp and repeat design, per-core workloads aren't always symmetrically balanced. For example, a cloud provider (AI or compute) will rent out individual core clusters to customers for specialized and varied workloads. However, this asymmetry, combined with rapid provisioning changes, can lead to global voltage droops on the SoC resulting in potenti... » read more

Advanced Design Planning In IC Compiler II
By Synopsys - 28 Feb, 2024 - Comments: 0

By Rajiv Dave, CAE Manager, Synopsys. Design exploration and planning is becoming an increasingly critical step of the design creation process as growing constraints and requirements are placed upon it. IC Compiler II has been architected from the ground up with the express focus to address the three key challenges of design planning: Capacity to handle the largest design optimally yet ... » read more

Integration Challenges For RISC-V Designs
By Ed Sperling - 27 Feb, 2024 - Comments: 0

One of the big draws of RISC-V is that it allows design teams to create unique chips or chiplets and to make modifications to the instruction-set architecture. That extra degree of freedom also creates some issues when it comes to integrating those designs into packages or systems because they may require non-standard connectivity approaches. Frank Schirrmeister, vice president of marketing at ... » read more

Thinking Big: From Chips To Systems
By Ed Sperling - 27 Feb, 2024 - Comments: 0

Semiconductor Engineering sat down with Aart de Geus, executive chair and founder of Synopsys, to talk about the shift from chips to systems, next-generation transistors, and what's required to build multi-die devices in the context of rapid change and other systems. SE: What are the biggest changes you're seeing in the chip industry these days, and why now? de Geus: It's not just the siz... » read more

Blog Review: Feb. 21
By Jesse Allen - 21 Feb, 2024 - Comments: 0

Siemens' John McMillan digs into physical verification maturity for high-density advanced packaging (HDAP) designs and major differences in the LVS verification flow compared to the well-established process for SoCs. Synopsys' Varun Shah identifies why a cloud adoption framework is key to getting the most out of deploying EDA tools in the cloud, including by ensuring that different types of ... » read more

Latency, Interconnects, And Poker
By Ed Sperling - 20 Feb, 2024 - Comments: 0

Semiconductor Engineering sat down with Larry Pileggi, Coraluppi Head and Tanoto Professor of Electrical and Computer Engineering at Carnegie Mellon University, and the winner of this year's Phil Kaufman Award for Pioneering Contributions. What follows are excerpts of that conversation. SE: When did you first get started working in semiconductors — and particularly, EDA? Pileggi: This w... » read more

Blog Review: Feb. 14
By Liz Allan - 14 Feb, 2024 - Comments: 0

Siemens’ Dilan Heredia and Karen Chow explain why fast, accurate parasitic extraction (PEX) is essential to design success, especially for the 3 nm node and GAAFETs. Synopsys’ Srinivas Velivala debunks the myth that layout-versus-schematic (LVS) checking is a static step in the chip development process, and details its evolving role in modern SoCs. Cadence’s Mark Seymour digs into a... » read more

Blog Review: Feb. 7
By Jesse Allen - 07 Feb, 2024 - Comments: 0

Synopsys' Ian Land, Kenneth Larsen, and Rob Aitken find that a new approach will be required to ensure that higher volume 3D heterogeneous integration (3DHI) designs can function reliably and successfully in aerospace, defense, and government systems. Siemens' John Golding provides a primer on the fundamental concepts related to signal integrity, including key topics such as transmission lin... » read more

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