The Quest For Curvilinear Photomasks

The semiconductor industry is making noticeable progress on the development of advanced curvilinear photomasks, a technology that has broad implications for chip designs at the most advanced nodes and the ability to manufacture those chips faster and cheaper.

The question now is when will this technology move beyond its niche-oriented status and ramp up into high-volume manufacturing. For years, the industry has been working on the development of complex curvilinear shapes on advanced photomasks using inverse lithography technology (ILT). These complex mask shapes can be incorporated on both optical and EUV photomasks, but bringing these technologies into mass production has been difficult. Optical and EUV masks based on more traditional rectangular shapes have been production for years.

Fig. 1: (L) TrueMask ILT curvilinear mask SEM for different pitches and orientations, and (R) corresponding wafer print SEM. Source: D2S

Curvilinear ILT masks aren’t new. They are one of several types of photomasks, which are critical components in the IC manufacturing supply chain. In the process flow, a chipmaker designs an IC, which is then translated into a file format. Then, in a photomask facility, a mask is developed based on that format.

The photomask is a master template for a given IC design. After a mask is developed, it is shipped to the fab. The mask is placed in a lithography scanner. The scanner projects light through the mask, which patterns the images on a wafer.

Today’s masks, including those based on optical and extreme ultraviolet (EUV) lithography, consist of tiny features that resemble rectangles, or so-called Manhattan shapes. In some cases, photomasks have simple curve or rectilinear shapes. At advanced nodes, though, chipmakers want more advanced masks.

That’s where curvilinear ILT masks fit in. In the works for nearly 15 years, ILT uses a mathematical formula to calculate the desired shapes on a photomask, which are free-form curvilinear types. ILT not only increases the process windows in chip manufacturing, but it also enables the best performance for a shape on the wafer. That’s important for small and complex features that are difficult to print.

But it’s still not easy. Curvilinear ILT technology requires an enormous amount of compute power to run the algorithms. It also requires the right mask-making equipment. Not all of the pieces are in place, either. So over the years, ILT technology has experienced some difficulties getting off the ground. It has been mainly used in niche-oriented applications like hot spots. This is where only a small portion of the mask layout requires ILT, while the remaining part uses traditional and simple features. On the other hand, curvilinear ILT masks are starting to take root in limited cases, especially in memory.

“Curvilinear ILT produces better process windows than what can be achieved with Manhattan features only,” said Harry Levinson, principal at HJL Lithography. “Curvilinear is not yet used in high-volume manufacturing. ILT has been used sparingly because of the long computation times required.”

Curvilinear shapes on all mask types are expected to become more pervasive by 2023, according to a survey from the eBeam Initiative. But to speed up the process, the industry is taking several measures, including:

• Intel, Samsung and TSMC as well as EDA vendors recently formed a working group, which is developing a new file format standard to deal with the complexities of curvilinear mask shapes. Several format standards have been proposed, and the group recently outlined the status of them.
• D2S has developed a compute system, enabling ILT designs in a day. Siemens, Synopsys and others have various ILT offerings.
• Intel’s IMS Nanofabrication unit and NuFlare are separately readying their next-generation multi-beam mask-writing systems to pattern complex masks, including curvilinear features.

Sub-wavelength era
In the 1990s, IC vendors were using 365nm wavelength lithography systems to pattern the features in chips. At the time, the lithographic process was relatively straightforward. The IC feature sizes were larger than the lithography wavelength.

By the mid-1990s, IC vendors moved to 248nm wavelength lithography scanners in chip production at the 250nm and/or 180nm node. Suddenly, the chip feature sizes became smaller than lithography wavelength, putting the semiconductor industry in the so-called sub-wavelength era.

This in turn increased the complexity of lithography and mask making, and required some major changes throughout the supply chain. First, the industry required a new data format standard. Up until 2004, GDSII was the de facto data file format standard in the semiconductor industry. As stated, in the flow, an IC design is translated into a data file format. The format represents the physical layout of a chip design.

GDSII, however, was limited. So in 2004, the industry developed a new data file format standard called the Open Artwork System Interchange Standard (OASIS). OASIS, which defines the code required for geometric shapes in chip design and manufacturing, is used in a large percentage of today’s chips.

The sub-wavelength era also required new innovations on the mask, such as resolution enhancement techniques (RETs). “(RETs are) designed to improve the usable resolution of an optical lithography tool of a given numerical aperture and wavelength,” explained Chris Mack, CTO of Fractilia.

One RET, called optical proximity correction (OPC), became a requirement starting at the 250nm node in 2001. OPC involves the formation of tiny assist features on the mask. These features don’t print on the wafer. Instead, they modify and boost the mask image patterns.

“OPC uses rule and model-based methods to modify layout shapes to compensate for lithographic non-linearity,” explained Peter Buck, director of MPC and mask defect management at Siemens Digital Industries Software.

Meanwhile, in the process flow, a file format (OASIS) is sent to a chipmaker, which handles the compute-intensive OPC process. From there, the data is sent to a photomask vendor, where the mask is made. Measuring 6 x 6 inches and ¼-inch thick, a traditional optical photomask consists of an opaque layer of chrome on a glass substrate.

To make a mask, the first step is to create a mask blank. Made by a mask blank vendor, the blank serves as the base structure of a mask. Once the blank is made, it is shipped to the photomask vendor. Then, at a photomask facility, a mask blank is patterned, etched, repaired and inspected, creating a mask with unique features.

The patterning step is critical. In this process, the blank is patterned using a mask writer system based on a given IC design. In the 2000s, the existing mask writers ran out of steam, prompting the industry to migrate to a new technology.

Starting in the 2000s, photomask makers embraced single-beam e-beam mask writer systems, based on variable shape beam (VSB) technology. “VSB writers use a pair of superimposed apertures to create a shot. The mask pattern is composed using rectangular and right triangle shots,” Buck said.

Each mask is different. An e-beam mask writer would take little time to pattern a simple mask. A complex mask takes a longer period. The industry uses the term “write times,” which determine how fast an e-beam can write a mask layer.

Nonetheless, mask makers plowed through the sub-wavelength era, at least initially. Using VSB mask writers and other equipment, photomask vendors were able to develop simple and complex masks.

Another innovation appeared in 2007, when a startup called Luminescent rolled out ILT technology. Considered an RET, ILT is a more complex form of OPC, enabling both rectilinear and curvilinear shapes on masks.

“(In ILT), you know something that you want to print. If you can model the scanner optics, then you can inversely calculate what’s on the mask. So that would give you the pattern fidelity and the best process window,” explained Leo Pang, chief product officer and executive vice president at D2S, in an interview several years ago. Pang was a former executive of Luminescent from 2004 to 2014. (Luminescent is no longer in business as a single entity. Parts of the company were acquired by Synopsys and KLA.)

ILT and OPC are slightly different. In OPC, you start with a simple pattern, and grate through pitch and feature sizes – a calibration structure of sorts, according to one expert. Then, you assess the printability on the wafer and create a model to generate artifacts that are placed in specific locations on the design pattern. This gives you the intended results on the wafer.

Regardless, ILT was ahead of its time, however. For one thing, it took an enormous amount of compute power to process ILT data. And using VSB mask writers, the write times for ILT took too long.

So ILT moved to the backburner. The industry didn’t give up on curve-like features, though. Under the OASIS standard, curvilinear shapes are recognized, but not fully developed. Basically, OPC can generate rectilinear and simple curve-like shapes.

Nonetheless, in the late-2000s, the shift towards OPC and other forms of RETs created more complex masks. And as a result, the e-beam mask writer tool took a longer time to pattern a mask, thereby impacting photomask turnaround times and costs.

From 2001 to 2005, e-beam write times were constant, averaging 8 hours per mask set. Then, from 2007 to 2012, the average write times increased to 10 hours. By the 2010s, the write times were 24 hours or more.

Multi-beam era
Fortunately, there was a solution. In 2016, IMS, a unit of Intel, unveiled the world’s first multi-beam mask writer. Unlike traditional VSB tools, which are single-beam systems, IMS’ multi-beam mask writer utilizes 262,144 tiny beamlets to speed up the write times for photomasks.

This system solves the write time issues. The write times for multi-beam tools are constant and take 12 hours or less for all masks. “You have a fixed write time independent of shot count or pattern complexity” said Naoya Hayashi, a research fellow at DNP, in a presentation at SPIE Advanced Lithography. “Multi-beam masks writers are essential for complex and high accuracy masks such as EUV masks.”

EUV, a next-generation lithography technology, patterns tiny features on chips using 13.5nm wavelengths. In 2018, chipmakers inserted ASML’s EUV scanners at the 7nm logic node in order to solve a major problem. Using multiple patterning, chipmakers extended traditional 193nm lithography down to 7nm. But at today’s 5nm process node, it’s too complex to use these techniques.

That’s where EUV fits in. EUV simplifies the process and enables chipmakers to pattern the most difficult features at 7nm and beyond. Today, select chipmakers are using ASML’s EUV scanners at 7nm and 5nm.

Like optical lithography, EUV also requires a photomask. But EUV masks are different. An EUV mask consists of thin alternating layers of silicon and molybdenum on a substrate. This results in a multi-layer stack that is 250nm to 350nm thick.

EUV masks are manufactured like optical masks. An EUV mask blank is developed, and then patterned using a multi-beam mask writer. Then, the structure is etched, repaired and inspected, creating an EUV mask.

Fig. 2: EUV mask fabrication steps. Source: Sematech

EUV masks are pattered using traditional shapes. “Today, an overwhelming majority of the shapes on the mask are Manhattan shapes, meaning axis-parallel straight edges and 90-degree corners, although there are some use of 45-degree edges,” said Aki Fujimura, chief executive of D2S.

While these shapes work for both optical and EUV masks, the industry now has its sights on a technology that was ahead of its time—ILT.

ILT era?
As before, the industry hopes to develop full-field curvilinear ILT masks. Both optical and EUV masks could consist of these curvilinear shapes.

Hotspot repair using ILT is also an option. In this case, a portion of the mask will require curvilinear shapes using ILT. The remainder of the mask would use traditional and simple shapes.

In all cases, ILT is an enabling technology. It promises to ease the constraints and enable the most difficult features, such as tiny contacts, cuts, and vias in IC designs. “Inverse lithography technology is an advanced form of optical proximity correction,” Fujimura said. “The objective is to design the mask shapes that will produce the best wafer performance for a given target design shape on the wafer. Wafer performance is measured by how closely the nominal shapes are projected to be on the wafer, and how resilient the shapes on the wafer are to manufacturing variation.”

Hotspot repair isn’t new, and has been used for years. Vendors have demonstrated full-field ILT masks. But these masks aren’t in mass manufacturing yet, although they are being used in limited cases for memory.

Curvilinear ILT masks may become more pervasive at 3nm/2nm in the 2023 timeframe. At 3nm/2nm, though, the challenges are enormous. At the 3nm node, the minimum feature size in devices is 12nm, compared to 15nm at the 5nm node, according to the IRDS roadmap.

Then, in the fab, EUV lithography is moving from single to double patterning at 5nm and beyond. “Multiple patterning in EUV is enabling, but does drive additional costs for customers,” said Richard Wise, vice president at Lam Research. “In addition, overlay continues as a challenge for EUV because the scaling causes the overlay targets to be more aggressive.”

Lithography isn’t the only challenge. “Post-5nm co-optimization of novel film, etch and clean technologies are critical to achieving cost-effective process integration,” said Kazuya Okubo, vice president of integrated solution planning at TEL, during a presentation at SPIE Advanced Lithography.

Nonetheless, there is a place for ILT. “Even for EUV, we still need to use dramatic mask corrections. A lot of times, the traditional Manhattan-shaped patterns are not good enough. The process windows and PV bands suffer if we stay with the Manhattan shapes. ILT actually comes into the rescue,” said Danping Peng, a director at TSMC, in a recent panel sponsored by the eBeam Initiative.

But several technologies must fall into place before curvilinear ILT mask technology moves into mass production, namely a new file format standard, more compute power, and advanced mask equipment.

First, the industry will require a new data file format standard for curvilinear technology. For one thing, the amount of data is exploding for EUV masks. Compared to optical lithography, the data volume per mask for EUV is increasing by 5X, according to a recent paper from Samsung and Siemens. The data volumes for curvilinear ILT are expected to increase even more, according to the paper.

OASIS, the current data format standard, recognizes curvilinear shapes, but it’s not sufficient to represent complex ILT data, according to the paper.

“Curvilinear provides better process latitude for small features. The dominant way to get to curvilinear structures is to use inverse lithography technology,” Siemens’ Buck said. “Curvilinear creates even larger volumes of data. Instead of having rectilinear shapes, now you have curvilinear shapes that have many small edge segments. This leads to a data volume explosion in the SEMI P44 (OASIS) layout format. That requires a new solution.”

In response, the industry in 2019 formed a new data format working group to address the need for curvilinear data representation. The group is driven by Samsung, TSMC, and Intel with representation from Siemens, Nippon Control Systems, D2S, Aselta, and ASML-Brion.

These companies plan to formalize the working group under SEMI. The goal is to develop a new file format standard based on curvilinear technology. A proposed standard wouldn’t replace OASIS, but rather it would be a sub-set of the current standard.

Today, the industry is looking at four approaches or possible standards here — quadratic Bezier, B-spline, polygon simplification, and curvature-based fragmentation (CBF).

Each one has a different way to represent curvilinear data. Quadratic Bezier and B-spline are curve-fitting methods. “Quadratic Bezier curves are defined by 3 control points,” according to the paper from Samsung and Siemens. “Quadratic B-Spline curves are piecewise curves where each component can be represented by a 2nd degree polynomial.”

“They are two approaches to represent curvilinear patterns more efficiently than piecewise linear polygons. Depending on the allowable fitting tolerance, we’re seeing compaction in the range of 2X to 8X compared to P44 OASIS using those methods,” Siemens’ Buck said.

On the downside, EDA tools from OPC through mask writing will need to be modified to support new curvilinear formats and a new or modified layout format needs to be defined.

In comparison, the polygon simplification and CBF leverage the OASIS approach. “These two approaches use standard P44 OASIS, so no new formats are required,” Buck said. “Insertion of polygon simplification or curvature-based fragmentation can be done within OPC or at read-in by MPC. Other tools in the post tape-out flow may not need to change. Polygon simplification approaches attempt to remove unnecessary vertices using metrics like edge position error and area loss. CBF, or curvature-based fragmentation, re-fragments shapes to co-optimize data volume, accuracy, and MPC runtime with fragment size based on local radius of curvature.”

So far, there is no consensus here. While the industry tries to hammer out a standard, other pieces need to fall into place before ILT masks are adopted. The processing or runtimes associated curvilinear ILT masks are too long, limiting the practical application of the technology.

In response, D2S recently rolled out a GPU-accelerated hardware and software system that enables stitch-less full-chip ILT for advanced designs in a day. That’s a good start, although the industry may require more horsepower for next-generation ILT masks.

If that’s not enough, the industry must manufacture curvilinear ILT masks at high volumes at acceptable costs. Basically, curvilinear ILT masks are manufactured like any other mask.

The patterning step would require a multi-beam mask writer. In fact, Intel’s IMS unit and NuFlare are readying their next-generation mask writers for the 3nm node.

IMS is shipping its second-generation tool—the MBMW-201, which is a 50KeV system with 262,144 beamlets. IMS is preparing to ship a new 50KeV version, dubbed the MBMW-301, which is targeted for 3nm. Meanwhile, after a false start with its initial multi-beam system, NuFlare is readying its next version. The MBM-2000 is a multi-beam tool with 16nm beamlets.

Besides mask writing, inspection is also important. Using inspection systems, photomask vendors want to look for defects on the mask. “Curvilinear design masks, as expected, are more challenging to inspect compared to standard masks,” said James Westphal, senior director at KLA. “In the mask shops, advanced systems that utilize die-to-database algorithms and leverage higher computation and storage capacity are needed to meet the requirement of more complex and computation-intensive database handling. In the IC fabs, die-to-gold reticle inspection technology is needed to address the pattern fidelity variation-induced nuisances from traditional die-to-die comparisons.”

Mask repair, the art of fixing mask defects on the fly in the mask shop, is also challenging. “The traditional hard defect and soft defect challenges in mask repair, brought about by contamination throughout the mask manufacturing process and reduction in mask features sizes, are expected to continue for mask technology at 3nm and beyond,” said Jeff LeClaire, director of technology and product development at Bruker.

Conclusion
Clearly, mask makers want curvilinear shapes on the mask, especially for EUV at 3nm and beyond.

Many of the ILT pieces are falling in place. There are still some gaps, which needs to be addressed.

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