category: Test, Measurement and Analytics

category: Auto, Security & Edge AI

HSIO Loopback Turns Challenges Into Opportunities For Test At 112 Gbps
By Dave Armstrong - 07 Dec, 2021 - Comments: 0

By Dave Armstrong and Don Thompson For both PCIe and Ethernet (IEEE 802.3,) signals are getting mighty small. With PCIe 5 reaching 32 Gbps (NRZ at 32 GBaud) and 802.3 reaching 112 Gbps (PAM4 at 56 GBaud), typical eye-mask limits are shrinking. Consequently, test requirements for high-speed I/O (HSIO) test are becoming daunting. HSIO test involves measurement of Tx eye height and width, co... » read more

Case Study — Deep Learning For Corner Fill Inspection And Metrology On Integrated Circuits
By CyberOptics - 07 Dec, 2021 - Comments: 0

CyberOptics utilized deep learning to accurately inspect the corner fill on integrated circuits (ICs) produced by a large memory supplier. Traditional methods of inspection showed limitations in their ability to entirely detect the presence and absence of fill, indicating that a more advanced approach was necessary. CyberOptics drew on its large pool of algorithm and neural network expertise to... » read more

Success Stories For Packetized Scan Data
By Geir Eide - 07 Dec, 2021 - Comments: 0

Some new design-for-test (DFT) technologies are difficult, expensive, or risky to implement but offer significant benefits. Other technologies are easy to implement but offer minor improvements. The calculation of whether (or when) to adopt new technology includes consideration of the pressures of DFT today—design complexity, the lack of flexibility in hardwiring scan channels, the proliferat... » read more

Big Payback For Combining Different Types Of Fab Data
By Anne Meixner - 07 Dec, 2021 - Comments: 1

Collecting and combining diverse data types from different manufacturing processes can play a significant role in improving semiconductor yield, quality, and reliability, but making that happen requires integrating deep domain expertise from various different process steps and sifting through huge volumes of data scattered across a global supply chain. The semiconductor manufacturing IC data... » read more

Extremely Large Exposure Field With Fine Resolution Lithography Technology To Enable Next Generation Panel Level Advanced Packaging
By Onto Innovation - 07 Dec, 2021 - Comments: 0

The growing demand for heterogeneous integration is driven by the 5G market that includes smartphones, data centers, servers, HPC, AI and IoT applications. Next-generation packaging technologies require tighter overlay to accommodate a larger package size with finer pitch chip interconnects on large format flexible panels. Heterogeneous integration enables next-generation device performance ... » read more

Engineers’ Experiences Around The World
By Ben Tsai - 07 Dec, 2021 - Comments: 0

As CTO, I see my role partially as strengthening the engineering community through program reviews, engineering education programs, conferences, seminars, and the product life cycle process at KLA. I also think it is critically important to spark engineering enthusiasm – helping engineers rediscover the excitement and curiosity that helps drive innovation. When inspired to create, engineers c... » read more

Enablers And Barriers For Connecting Diverse Data
By Anne Meixner - 09 Nov, 2021 - Comments: 0

More data is being collected at every step of the manufacturing process, raising the possibility of combining data in new ways to solve engineering problems. But this is far from simple, and combining results is not always possible. The semiconductor industry’s thirst for data has created oceans of it from the manufacturing process. In addition, semiconductor designs large and small now ha... » read more

Reversible Chain Diagnosis
By Siemens EDA - 09 Nov, 2021 - Comments: 0

For advanced technologies, the industry is seeing very complicated silicon defect types and defect distribution. One consequence is that scan chain diagnosis becomes more difficult. To improve the resolution of scan chain diagnosis, Tessent Diagnosis can use new scan chain test patterns to leverage a reversible scan chain architecture. This paper describes the novel scan chain architecture t... » read more

More Errors, More Correction in Memories
By Bryon Moyer - 09 Nov, 2021 - Comments: 1

As memory bit cells of any type become smaller, bit error rates increase due to lower margins and process variation. This can be dealt with using error correction to account for and correct bit errors, but as more sophisticated error-correction codes (ECC) are used, it requires more silicon area, which in turn drives up the cost. Given this trend, the looming question is whether the cost of ... » read more

Coping With Parallel Test Site-to-Site Variation
By Anne Meixner - 09 Nov, 2021 - Comments: 1

Testing multiple devices in parallel using the same ATE results in reduced test time and lower costs, but it requires engineering finesse to make it so. Minimizing test measurement variation for each device under test (DUT) is a multi-physics problem, and it's one that is becoming more essential to resolve at each new process node and in multi-chip packages. It requires synchronization of el... » read more

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