Stanford’s ‘Intelligence per Watt’; ultrafast chip bonding; optimized RISC-V multi-core processor; capacitive In-memory-computing; architectural rowhammer defenses; HW-in-the-loop driving simulators; growth of highly-crystalline wafer-scale vdW thin films by MBE; agentic AI safety for EdgeAI.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Intelligence per Watt: Measuring Intelligence Efficiency of Local AI | Stanford University, Together AI |
| Ultrafast Semiconductor Chip Bonding Using Intense Pulsed Light Soldering for Chip-on-Glass Packaging | Sungkyunkwan Univ., Chungbuk National Univ. |
| MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference | FZI, KIT |
| Toward Capacitive In-Memory-Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware | Tampere Univ. |
| SoK: Systematizing a Decade of Architectural RowHammer Defenses Through the Lens of Streaming Algorithms | Meta, Seoul National Univ., UIUC |
| Hardware-in-the-Loop Driving Simulators: Simplifying Real Component Integration in Simulated Environments | Università degli Studi di Firenze, Meccanica 42 |
| 3D Guard-Layer: An Integrated Agentic AI Safety System for Edge Artificial Intelligence | Princeton Univ., HKUST, NC State Univ. |
| Mitigation of Structural Defects during the Growth of 2D van der Waals Chalcogenides by Molecular Beam Epitaxy | Penn State Univ. |
Find more semiconductor research papers here.
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