Gearing Up For High-NA EUV

The semiconductor industry is moving full speed ahead to develop high-NA EUV, but bringing up this next generation lithography system and the associated infrastructure remains a monumental and expensive task.

ASML has been developing its high-numerical aperture (high-NA) EUV lithography line for some time. Basically, high-NA EUV scanners are the follow-on to today’s EUV lithography systems based on a 0.33 NA lens. Still in R&D, ASML’s new high-NA EUV system involves a completely new tool, featuring a 0.55 NA lens capable of 8nm resolutions, compared to 13nm for the existing tool. The 0.55 NA EUV tool is targeted for 3nm in 2023, but it’s unlikely to move into production until 2025, analysts said.

A high-NA scanner is expected to cost $318.6 million, compared to $153.4 million for today’s EUV systems, according to KeyBanc. The total cost is even higher. Other new equipment, new photomasks, and different photoresists are required to enable high-NA EUV. Various vendors are working on these technologies, but at this point some gaps remain.

Lithography equipment is used to pattern tiny features on chips, enabling chipmakers to develop smaller and faster devices at advanced nodes, and to pack more features into a single die or package. Until 2018, chipmakers patterned the features on leading-edge chips using traditional optical lithography scanners. But at advanced nodes, the patterning process with optical lithography became too complex, prompting the need for EUV. Now even that’s not sufficient.

Utilizing a 13.5nm wavelength, ASML’s 0.33 NA EUV scanners are being used by Samsung and TSMC to produce 7nm and 5nm chips. Intel is also inserting ASML’s EUV scanners for advanced chip production. Samsung and SK Hynix are using EUV for DRAM production.

Chipmakers will use today’s EUV for a long time. But at some point — somewhere beyond the 3nm node — it will become difficult to pattern future chips using existing EUV. This is where high-NA fits in. Intel, for one, believes the technology is critical and announced plans to install ASML’s first 0.55 high-NA EUV scanner.

“It will bring a significant amount of learning, but it also will enable us to continue the progression down to the smallest geometries,” said Ann Kelleher, senior vice president and general manager of Technology Development at Intel.

Samsung and TSMC also will buy high-NA tools. But the transition toward high-NA EUV involves an assortment of new and moving parts. “High-NA re-uses a lot of knowledge from 0.33 NA EUV,” said Krish Sankar, an analyst at Cowen. “Introduction of EUV was more challenging for resists. Migration to high-NA is more evolutionary, and the resists will continue to improve in performance to meet the imaging requirements on future nodes. The optics are new for high-NA, but they are still reflective optics.”

Why high-NA?
In a fab, chipmakers utilize lithography and other equipment to produce chips. Using a file format generated in the design phase, a photomask facility creates a mask. The mask is a master template for a given chip design, and eventually is shipped to the fab. From there, wafers are inserted into a coater/developer system. The system pours a light-sensitive material called a photoresist onto a wafer.

Then, the mask and wafer are inserted in a lithography scanner. In operation, the scanner generates light, which is transported through a set of projection optics and the mask in the system. Light hits the resist, creating patterns on the wafer.

Fig. 1: Example of a typical sequence of lithographic processing steps. Source: Chris Mack, Fractilia

For years, chipmakers used optical-based 193nm wavelength lithography tools to pattern advanced chip features. With various techniques, chipmakers extended 193nm lithography down to 7nm. But at 5nm, it’s too complex to use these techniques.

“Trying to print 50nm, 40nm or 30nm features is an inherently difficult task for 193nm lithography,” said Aki Fujimura, chief executive of D2S. “Using EUV at 13.5nm wavelengths should make it easier and more viable.”

In 2018, Samsung and TSMC inserted ASML’s 0.33 NA EUV scanners for use in manufacturing chips at 7nm, and most recently at 5nm. ASML’s EUV scanners enable 13nm resolutions with a throughput from 135 to 145 wafers per hour (wph).

But EUV isn’t perfect. The process sometimes can cause unwanted variations and defects. System uptime is an issue, as well.

Nonetheless, at 7nm, chipmakers are using EUV to pattern chip features with pitches starting at 40nm. Vendors are using an EUV-based single patterning approach. The idea is to put the chip features on one mask and print them on the wafer using a single lithographic exposure.

Chipmakers want to extend EUV single patterning as far as possible. EUV single patterning reaches the limit at 32nm to 30nm pitches, which represents the 5nm node or so.

At those pitches and beyond, roughly at the 3nm node, chipmakers need to look at new options, namely EUV double patterning. In double patterning, you split the chip features on two masks and print them on the wafer. This is complex and expensive, but it’s also something the fabs have mastered with 193nm lithography.

Some may want to avoid EUV double patterning altogether. “Now we are coming close to the limits of 0.33 NA EUV single exposure and high-NA EUV is being considered,” said Arnaud Dauendorffer, a process engineer from TEL, in a presentation at the recent SPIE Photomask Technology + EUV conference.

To avoid EUV double patterning, chipmakers are pushing for high-NA EUV at 3nm and beyond. High-NA EUV promises to enable the simpler single-patterning approach.

“The tool provides more resolution. So that means that you can print more features with it. The aerial image contrast allows for better local CD uniformity,” said Jan van Schoot, director of system engineering at ASML, during a presentation at the conference.

ASML’s first high-NA EUV system, the EXE:5000, features 8nm resolutions with a throughput of 150 wph. Customer shipments are slated for 2023. Then, at the end of 2024, ASML will ship a new version, the EXE:5200, which has a throughput of 220 wph.

High-NA EUV works like today’s EUV lithography, but there are some key differences. Instead of a traditional lens, the high-NA tool incorporates an anamorphic lens, supporting 8X magnification in one direction and 4X in the other. So the field size is reduced by half. In some cases, a chipmaker would process a chip on two masks. Then the masks are stitched together and printed on the wafer, which is a complex process.

New masks
High-NA EUV also requires new photomask types. EUV and traditional optical masks are different. Optical masks consist of an opaque layer of chrome on a glass substrate, which makes them transmissive to light.

There are several types of optical masks, such as binary and phase-shift masks (PSMs).

Fig. 2: A schematic illustration of various types of masks: (a) a conventional (binary) mask; (b) an alternating phase-shift mask; (c) an attenuated phase-shift mask. Source: Wikipedia

In binary masks, chrome is etched in select places, which exposes the glass substrate. The chrome materials aren’t etched in other places. In operation, light hits the mask and goes through the areas with the glass, which exposes the wafer. Light doesn’t go through the areas with the chrome.

PSMs are also used today. “There are many flavors of PSM, but they work by using phase to cancel light where you don’t want it, thus producing a higher contrast image,” said Chris Mack, CTO of Fractilia.

Today’s EUV masks are binary and reflective. An EUV mask and/or blank consists of 40 to 50 thin alternating layers of silicon and molybdenum on a substrate. This results in a multi-layer stack that is 250nm to 350nm thick. On the stack, there is a ruthenium-based capping layer, followed by an absorber based on a tantalum material.

Fig. 3: Cross-section of an EUV mask. Source: Luong, V., Philipsen, V., Hendrickx, E., Opsomer, K., Detavernier, C., Laubis, C., Scholze, F., Heyns, M., “Ni-Al alloys as alternative EUV mask absorber,” Appl. Sci. (8), 521 (2018). (Imec, KU Leuven, Ghent University, PTB)

In mask production, the first step is to create a substrate or mask blank. Made by a mask blank vendor, the blank serves as the base structure of a mask.

To make EUV mask blanks, a vendor deposits alternating layers of silicon and molybdenum onto the substrate. The mask blank is inspected for defects using actinic and optical inspection equipment.

Lasertec sells an actinic blank inspection (ABI) system for EUV mask blanks. Using a 13.5nm wavelength, the ABI tool has 1nm (height) x 40nm (width) sensitivities with a defect location accuracy of 20nm.

For high-NA EUV, Lasertec is developing a new ABI system with 1nm x 30nm sensitivities. “We are targeting 10nm for the defect location,” said Masashi Sunako, president of Lasertec USA, in a presentation at the conference.

On top of that, the industry is developing new EUV mask types for 3nm and beyond. In today’s EUV masks, the absorber is a 3D-like feature that juts out on top of the mask. In operation, EUV light hits the mask at a 6° angle. The reflections potentially cause a shadowing effect or photomask-induced imaging aberrations on the wafer. This issue, known as mask 3D effects, can result in unwanted pattern placement shifts.

To mitigate these effects, the EUV mask requires a thinner absorber. In existing EUV masks, the tantalum absorber is 60nm thick. It can be made thinner, but the limit at 50nm, which doesn’t solve the mask effects. In response, the industry is developing several new EUV mask types, such as 2D, absorberless, high-k, non-reflecting and PSM.

EUV PSMs appear to have the most momentum. This technology addresses the mask 3D effects while also improving image quality with better contrast.

But EUV PSMs may require different materials. In a presentation at the SPIE Photomask/EUV conference, Hanyang University researchers described a phase-shift EUV mask, which consists of alternating layers of ruthenium and silicon on a substrate. A ruthenium capping layer is situated on top of the multi-layer structure, followed by a tantalum-boron etch stopper, and a ruthenium alloy as the phase-shift material.

In a paper, Hoya developed various attenuated phase-shift type absorbers and evaluated the properties. “PSM expects to bring imaging gain,” said Ikuya Fukasawa from Hoya, in a presentation. “But in order to develop EUV PSM blanks, we have to meet a lot of requirements. The absorber material must have small roughness and high durability against mask cleaning. And of course, the absorber has to be etched on a mask process.”

Like EUV PSMs, high-k masks are also in R&D. A high-k EUV mask resembles today’s EUV masks. Instead of a tantalum absorber, the industry is exploring other materials like nickel. A thinner nickel absorber could mitigate the mask effects, but this material is difficult to work with.

Meanwhile, startup Astrileux recently described a new non-reflecting EUV mask using a ruthenium material. “Our mask is darker in the dark regions, and brighter in the clear regions, and overall has less background illumination and leakage,” said Supriya Jaiswal, CEO of Astrileux.

Astrileux also described a 2D mask, where the absorber is incorporated within the blank. The startup also talked about an aborberless mask. All of these are in R&D.

As it stands today, chipmakers will continue to use the existing EUV mask/blank structure for existing 0.33 NA EUV tools. Then at some point chipmakers will likely insert EUV PSMs for 0.33 EUV. When high-NA EUV is ready, chipmakers likely will use PSMs. High-k and other mask types are also possibilities.

“There are several approaches as you go forward, whether it’s phase-shift, low-n or high-k,” said Geoff Akiki, president of Hoya LSI at the Hoya Group. “The real trick here will be integration and making it work in manufacturing, getting it out the door as a product. For instance, you have things like flatness, which we spend a lot of time worrying about. You have defects, which we all talk about. In a sense, the selection of all these things is like trying to tune a process window. It’s what gets you to the thing that’s usable at the end, not under ideal conditions.”

New mask equipment
Meanwhile, once the mask blank is made, it is shipped to the photomask vendor. At the mask supplier, a blank is patterned, etched, repaired and inspected. Finally, a pellicle is mounted on the mask.

Fig. 4: EUV mask fabrication steps. Source: Sematech

First, photomask makers use a system called an e-beam mask writer to write patterns on the mask based on a given IC design. For years, mask makers relied on a single-beam e-beam tool, based on variable shape beam (VSB) technology. In operation, a mask is inserted in the system and electrons hit the mask in form of shots.

VSB-based mask writers work for traditional optical masks. But EUV masks have smaller and more complex features, and VSB is too slow to pattern them.

For EUV and some complex optical masks, mask makers use multi-beam mask writers. IMS Nanofabrication’s multi-beam mask writing tool utilizes 262,000 tiny beams, which speeds up the process. The write times are constant, taking 12 hours or so to pattern all masks.

IMS is shipping its second-generation tool with a new version in R&D. “For high-NA EUV mask manufacturing, the new MBMW-301 tool will be provided with a higher number of beams,” said Hans Loeschner, a senior advisor at IMS.

NuFlare also is developing a multi-beam mask writer. These systems are targeted to pattern next-generation EUV and curvilinear masks. The industry is also developing curvilinear shapes on advanced photomasks using inverse lithography technology (ILT). So-called ILT masks will become important for EUV, especially high-NA.

“ILT masks are a way to enhance process windows to improve the resilience of a wafer production process to manufacturing variation,” D2S’ Fujimura said.

After the patterning step, the mask structure is etched and cleaned, forming a photomask. During the production process, defects can crop up on the photomask.

This can be problematic. In the lithographic process, the light from a scanner passes through the photomask, which projects the desired images onto the wafer. If the mask has a defect, the irregularities might get printed on the wafer. This can impact yield of a die, and it could even kill a chip.

So during the mask-making process, the photomask must be inspected for defects. For traditional optical masks, photomask makers use optical mask inspection systems. Applied Materials, KLA, Lasertec and NuFlare sell these systems.

Optical inspection tools also can inspect EUV masks. The problem with optical is resolution. They may run out of steam at 20nm to 16nm half-pitch resolutions.

In response, Lasertec recently introduced an actinic patterned mask inspection (APMI) system using a 13.5nm source. The smaller wavelengths enable the system to locate sub-20nm defects for EUV masks.

Lasertec also is developing an APMI system for high-NA EUV masks. “The new optics, the detector and the system design are completed,” Lasertec’s Sunako said. This tool is slated for 2023/2024.

Beside optical and APMI, customers will have another option for EUV mask inspection. KLA and NuFlare are developing multi-beam e-beam mask inspection tools.

NuFlare is developing a multi-beam inspection system with 100 beams, which is slated for 2023. “Sensitivity is 15nm. Inspection time is 6 hours per one mask inspection period,” said Tadayuki Sugimori of NuFlare.

All told, for current and future EUV masks, photomask makers will use all inspection types—actinic, e-beam and optical.

Like inspection, mask repair is also critical. If a mask has defects, a photomask maker can repair them using a mask repair system. There are two types of mask repair tools, e-beam and nanomachining. Both are complementary.

For advanced nodes, Zeiss introduced a new mask repair tool using e-beam technology. The system repairs defects down to 60nm half-pitch on masks and extrusions of 10nm and smaller.

Meanwhile, Bruker supplies mask repair tools using nanomachining techniques. These systems incorporate a tiny tip to repair mask defects.

All mask repair tools must keep pace with the shrinking feature and defect sizes at advanced nodes. They must also deal with various materials. “The material independence of these processes is critical for the removal of fall-on and other residual soft defect contamination as the materials properties are most often unknown,” said Jeff LeClaire, director of technology at Bruker.

Wanted: New resists
Photoresists are also critical for lithography. Chipmakers want resists with good resolution [R], low line-width roughness [L], and sensitivity [S].

The industry has developed resists for optical lithography, which falls within the RLS targets. But it’s a different story for EUV resists. “Obtaining all three of these at the same time is difficult, as they are interrelated, and improvements in one parameter generally degrades at least one of the others–often referred to as the RLS trade-off relation,” said Rich Wise, vice president at Lam Research, in a blog.

EUV resists, which are in production, are based on two technologies— chemically amplified resists (CARs) and metal oxide. Used for both optical and EUV, CARs involve a complex process. When photons hit the resists in the scanner, it causes a chain reaction.

“Part of the reaction cascade involves a chemical amplification of the initial photon, where the photon is first converted into several electrons, whereby several photoacid molecules are eventually generated per incident photon,” Wise said. “The advantage of CAR is that resist sensitivity can be increased by increasing the number of photoacid molecules that are generated per photon. However, these additional acids will be located further and further from the site of the original photon, resulting in image blur, which reduces resolution and increases line-edge roughness.”

Metal oxide resists are less mature, but they have some advantages. For example, Inpria’s metal-oxide photoresists are based on a tin-oxide structure, which captures EUV photons more efficiently.

Today, the industry is searching for a resist that meets the RLS requirements for high-NA EUV. That’s still a work in progress. Researchers at the Paul Scherrer Institute (PSI) and ASML are screening various resists for high-NA using an interference EUV lithography system. Researchers patterned lines and spaces with various resists, hoping to obtain 8nm half-pitch resolutions.

PSI recently presented the results from CAR and non-CAR resists from undisclosed suppliers. Using a dose around 60mJ/cm² for the CARs, PSI’s R&D EUV system patterned clear lines and spaces at 13nm half-pitch, but it encountered minor bridging at 12nm and a pattern collapse at 11nm. “We’ve pushed the ultimate resolution of the chemically amplified resist from 12nm in one case to 11nm, simply by optimizing the underlayer,” said Timothée Allenet, a researcher from PSI, in a presentation.

Meanwhile, with a 30mJ/cm² dose, molecular resists demonstrated good images at 13nm, but they encountered failures due to pattern collapses at 12nm, according to PSI.

Then, using various doses, metal-oxide resists demonstrated good results down to 12nm. “At 11nm half-pitch, we have minor bridging, and then we have a resolution bottleneck at 10nm,” Allenet said.

On the bright side, today’s resists for 0.33 NA EUV aren’t standing still and are improving. For example, TEL described new processes for CARs and metal oxide resists. “In summary, coater/developer processess together with the optimized underlayer film shows improvement in pattern collapse margin for CAR. Optimized underlayer improved defect density, yield, and roughness for metal oxide resists,” said Kanzo Kato at TEL.

Conclusion
Other EUV technologies are also in the works, such as pellicles. Pellicles are used to cover a mask, preventing particles from landing on the mask.

ASML has developed new EUV pellicles. Meanwhile, Imec’s carbon nanotube pellicles have demonstrated 97.7% transmissions on ASML’s EUV scanners. Both single- and multi-wall pellicles are promising. “Both types performed well showing minimal imaging differences over the no-pellicle reference for CD uniformity, LWR and flare. The minor increase in dose was anticipated based on measured EUV absorption that ranged from 95.3% to 97.7% on these pellicles,” said Emily Gallagher, a principal member of technical staff at Imec.

Other technologies are being developed for high-NA EUV. Regardless of whether all the pieces are in place, chipmakers say high-NA EUV is needed for chip production at 2023 and beyond. Still, the R&D costs are just beginning to pile up. Not many can afford these systems. And yet to be seen is when high-NA will really move into production.

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