Progress on 3D-ICs, using HBM with fan-outs, and other new approaches.
A new wave of 2.5D/3D, fan-out and other advanced IC packages is expected to flood the market over the next year.
The new packages are targeted to address many of the same and challenging applications in the market, such as multi-die integration, memory bandwidth issues and even chip scaling. But the new, advanced IC packages face some technical challenges. And cost remains an issue as advanced packaging is still relatively expensive for the masses.
It’s difficult to list all of the new package types on the horizon, but here are some of the major technologies coming down the pike:
Each technology is geared toward a different application. Generally, though, the idea behind these and other advanced package types is to integrate multiple die in the same package, which is a form of heterogeneous integration. This, in turn, enables the package to perform a specific and advanced function in a small form factor.
Heterogeneous integration has other implications, as well. It is becoming an alternative to IC scaling. Packing more transistors on a monolithic IC is becoming more difficult and expensive at each node. Another way to get the benefits of scaling is by putting multiple and advanced chips in an IC package.
Addressing the ongoing memory bottleneck issues in systems is another driving force behind advanced packaging. In systems, data moves between the processor and memory. But at times this exchange causes latency and power consumption, which is sometimes called the memory wall.
“The world is driving more data in systems. So, processors need large amounts of memory. And the memory and processor need to be very close,” said Rich Rice, senior vice president of business development at ASE. “So, you need packaging solutions that enable it, whether it’s 2.5D or a fan-out with a substrate approach. This could also be PoP structures like package-on-package. You are putting a mobile memory on top of an application processor, but you are doing it with very dense interconnects.”
Regardless of the technology, the industry needs to keep a close eye on IC packaging. The overall IC packaging market is projected to reach $68 billion in 2019, up 3.5% over 2018, according to Yole Développement. Of those figures, advanced packaging is projected to grow at 4.3% in 2019, compared to 2.8% for traditional/commodity packaging, according to Yole.
More 2.5D/3D and chiplets
IC packaging is important for several reasons. First, a package encapsulates a chip, preventing it from being damaged. A package also connects the device to a board.
Second, smartphones and other products require chips with small form factors. This requires small, fine-pitch packages with good electrical performance.
Third, in some cases, OEMs require a small, multi-die package that performs a specific function, sometimes known as a systems-in-package (SIP). For example, you may need to integrate a communications device with some control circuitry for an IoT or sensing application. “On the SIP front, you are also going to see a lot of heterogeneous integration,” ASE’s Rice said.
Fourth, customers continue to embrace advance packaging to solve various issues. “Advanced packaging technologies, such as 2.5D, 3D TSV, high-density fan-out, and low-density fan-out, will continue their current courses. We will continue to see incremental improvements in materials, thinness and electrical performance in all sectors of packaging,” said Ron Huemoeller, corporate vice president of R&D at Amkor.
For years, the industry has been developing advanced packages to address other challenges in systems, such as the memory wall. In today’s memory hierarchy, SRAM is integrated into the processor for cache. DRAM, which is used for main memory, is separate and located in a dual in-line memory module (DIMM). And disk drives and NAND-based solid-state storage drives (SSDs) are used for storage.
Today’s memory hierarchy has some challenges, especially at the high end. “Customers in AI, machine learning and the data center space are facing challenges where they can’t get enough access to memory. That can be memory on chip or can be memory off chip, off package,” explained David McCann, vice president of post fab development and operations at GlobalFoundries, in a video. “What that is doing for the on-chip memory is driving the die size up. It makes the cost increase.”
To help solve the problem for high-end applications like servers, the industry is moving toward 2.5D technologies. In 2.5D, dies are stacked on top of an interposer, which incorporates through-silicon vias (TSVs). The interposer acts as the bridge between the chips and a board, which provides more I/Os and bandwidth.
In one example of a 2.5D package, a vendor could incorporate an FPGA and HBM. Targeted for high-end systems, HBM stacks DRAM dies on top of each other, enabling more I/Os. For example, Samsung’s latest HBM2 technology consists of eight 8Gbit DRAM dies, which are stacked and connected using 5,000 TSVs.
In total, it enables 307GBps of data bandwidth. In comparison, using conventional DRAM, the maximum bandwidth of four DDR4 DIMMs is 85.2GBps, according to Xilinx. In most versions of 2.5D, the chips are situated side-by-side, although there is some development underway in using “pillars” on top of those chips. But in either case, the memory resides closer to the processor than it would in a classical planar design, and the throughput to external memory is faster.
“We are addressing the memory latency problem by bringing that memory very close and creating a massively parallel interface between the chips,” McCann said, noting that the downside is that the interposer is relatively expensive. “That adds cost, but it enables us to have dense interconnects between chips.”
Beyond 2.5D, the next big leap is 3D-ICs or vertical stacking, which promises faster access and lower latency between the memory and processor.
3D is an overused term that means different things to different people. Some call 2.5D a 3D technology. Technically, a DRAM stack, which has been wire-bonded, is also 3D.
“Traditionally, 3D-IC means something with a through-silicon via through an active die. People are taking that in different directions,” ASE’s Rice explained. “Then, there are passive interposers. There are also active interposers with some level of circuitry or functionality. You are placing a die on top of that. The interposer is active, meaning that it might have some power circuits or memory.”
3D-IC technology is not new. It has been in development for years. In 2011, for example, Micron announced the Hybrid Memory Cube (HMC), which stacks memory dies on a logic chip. In 2018, Micron dropped the HMC due to lackluster adoption.
Another form of 3D-IC is stacking logic dies on each other. “3D logic to logic is not new. There are lots of R&D prototypes from various players, but no production yet,” said Santosh Kumar, an analyst at Yole. “Cost, of course, is the main challenge. But there are technical issues as well, such as thermal management, known-good die, testing and reliability.”
There appears to be progress on many of these issues, which could finally make 3D-ICs a reality. Vendors now are talking about various products in the arena. For example, GlobalFoundries is developing an “SRAM cube.” Generally, SRAM is integrated with the processor, but SRAM takes up an inordinate amount of real estate. Instead of integrating SRAM with the processor, an SRAM die is stacked on top of the processor and connected with TSVs. The resulting device is an SRAM/logic stack.
The goal is to shorten the interconnect distance between the processor and SRAM, thereby reducing the latency. “We now have chips that are smaller,” GlobalFoundries’ McCann said. “The overall cost can drop significantly.”
Beyond that, GlobalFoundries also is developing a combination of 2.5D/3D technology, which promises to enable even faster access to memory. For example, in a 2.5D package, you would place three separate memory stacks on an interposer. The first one is an SRAM cube, which is situated between two HBM stacks on the interposer.
Meanwhile, Intel recently launched a new 3D packaging technology called “Foveros.” This is not one product, but rather it serves as a technology to enable multi-die packages. It allows chips to be broken up into smaller IP blocks or chiplets, which are connected using an active interposer.
Intel says it has solved the technical hurdles that have hampered 3D-ICs. “The first thing is solving the two or three intractable problems like thermal and power delivery. It’s a challenge and hasn’t been easily solved. We’ve come up with new innovations to solve that,” said Wilfred Gomes, a senior principal engineer at Intel.
All told, Intel’s Foveros enables more advanced forms of heterogeneous integration, if not a different way to scale a device. On paper, the technology could match the functionality of an integrated system-on-chip (SOC), according to Intel.
Intel hasn’t given up on chip scaling, but Foveros provides some new options. For example, using this approach, Intel recently unveiled a new hybrid CPU platform, code-named “Lakefield.” This combines a 10nm processor core with four of Intel’s Atom processor cores into a tiny package.
Intel and others are paving the way toward the chiplets model. In chiplets, the idea of putting together different modules like LEGOs has been talked about for years, but few have implemented it.
“The motivation for chiplets is to work in smaller technology increments by either leveraging existing functionality in existing silicon, or creating smaller building blocks that can be mixed and matched as needed for better system optimization, lower costs and faster time-to-market,” said Amin Shokrollahi, chief executive of Kandou Bus. “Chiplets will open a whole new era of silicon innovation and make it easier for smaller players to compete.”
Kandou Bus has developed an interconnect fabric, which serves as a die-to-die interconnect for chiplets in a package or module. The company is working with several groups in the arena.
So when will chiplets take off? “Many prototypes have already been built for products that use our Glasswing SerDes technology and we anticipate volume production by middle 2019,” Shokrollahi said. “But broad industry adoption of a chiplet strategy and development of interoperable chiplets is probably still a couple of years away.
“There are still many questions about how to design, manufacture, assemble and test chiplets and then support these solutions in the field. There are additional challenges when chiplets come from different companies or are manufactured in different foundry processes. Kandou has worked through some of the interface issues, at least from a SerDes perspective, but we definitely see a need for broader industry engagement and cooperation to create a common framework,” Shokrollahi said.
Yaniv Koppelman, networking CTO at Marvell Semiconductor, agrees. “Today, we are using all kinds of chiplets on switches, and you can populate many types of feeds and speeds with different amounts of chiplets. What we found, though, is the industry is still not ready for this approach technologically. We have not yet hit critical mass. This is why you’re starting to see XSR (extra short-reach), which is an interface from 100-gig PAM-4 that you can shrink. We’re also seeing options for in-package optics, which may drive a standard interface between two chips, although not necessarily in the same company.”
More fan-outs
Meanwhile, momentum is building for another packaging technology called fan-out wafer-level packaging (FOWLP). In fan-out, the dies are packaged while on a wafer. Fan-out doesn’t require an interposer, making it cheaper than 2.5D/3D.
But packaging customers want HBM, and HBM was only available in 2.5D/3D packages. That is likely to change. The industry currently is working on high-density fan-out packages that integrate and support HBM. These packages could give customers a new and cheaper option for HBM technology.
With or without HBM, fan-out involves the same basic structure. “In FOWLP, chips are embedded inside epoxy molding compound and then high-density redistribution layers (RDLs) and solder balls are fabricated on the wafer surface to produce a reconstituted wafer,” explained Kim Yess, technology director for the Wafer Level Packaging Materials business unit at Brewer Science, in a blog.
RDLs are the copper metal connection lines or traces that electrically connect one part of the package to another. RDLs are measured by line and space, which refer to the width and pitch of a metal trace.
There are three types of fan-out packages—chip-first/face-down; chip-first/face-up; and chip-last or RDL first.
Initially, fan-out didn’t incorporate a substrate as a base material. At times, though, a substrate-less fan-out package is prone to warpage and/or stress due to a mismatch between the dies and the epoxy mold compound.
So recently, packaging houses began to develop fan-out on substrate. The flow is similar, but the package uses a BGA substrate, which boosts the reliability of the device. “There are multiple methods to incorporate wafer-based fan-out technologies onto a substrate platform,” Amkor’s Huemoeller. “The use of both low-density and high-density are being employed today depending on die pitch and electrical performance requirements. Both are more typically placed onto current substrates that contain fewer layers with larger features, allowing both reduction in cost and a broader supply chain. These are typically BGA substrates, but HDI boards are being considered.”
In 2016, for example, ASE introduced a technology called Fan Out Chip on Substrate (FoCoS). Targeted for servers, the first customer for FoCoS incorporated separate 16nm and 28nm dies in the same package. The package has four metal layers with a 2-2.5µm line/space configuration.
The initial FoCoS package is based on a chip-first flow. Slated for this year, the next-generation FoCoS supports HBM. This version is capable of 2-2µm line/space, with 1.5-2µm due out in the future.
“ASE is working with customers for a chip-last version of FoCoS, which can support HBM2 memory,” said John Hunt, senior director of engineering at ASE. “It is intended for heterogeneous and homogeneous server applications, as well as AI and chiplet applications. It is intended to be an alternative to an interposer solution for these markets. It provides a lower cost solution, and actually has better electrical and thermal performance than a silicon interposer structure.”
FoCoS makes use of a BGA substrate. “It is basically the same type of substrate used on a standard BGA package, as well as the same used for a 2.5D interposer package,” Hunt said. “The BGA substrate provides the second level of ‘fan out’ of the package from the finer FoCoS bump pitch to a standard circuit board assembly pitch with an effective cost structure.”
TSMC, meanwhile, is moving in a similar direction. TSMC’s fan-out packaging technology, called InFO, is being used in Apple’s latest iPhones. Now, the foundry giant is developing a new InFo on substrate technology, dubbed InFO_MS. “InFO_MS is the one that supports HBM,” said Jan Vardaman, president of TechSearch International. “It should be in production this year.”
“Although InFO_MS is in the early stages of R&D, this technology is meant to integrate HBM onto a substrate directly without an interposer. But it is not easy to achieve this technically,” said Favier Shoo, an analyst at Yole.
TSMC also is developing an ultra-high density version of InFO, which brings fan-out into the sub-µm regime. Until now, the most advanced fan-out had RDLs down to roughly 2-2µm line/space. However, TSMC is readying InFO at 0.8µm with finer geometries in R&D. “It’s the same architecture. This interconnect density is important for bandwidth improvement. We’ve also minimized the parasitics whenever possible,” said Doug Yu, vice president of R&D at TSMC.
There are other benefits. “Redistribution layers with smaller critical dimensions enable reducing the total number of redistribution process levels in a fan-out package. This in turn reduces the total packaging cost and improves yield,” said Warren Flack, vice president of worldwide lithography applications at Veeco. “Currently, 1µm RDL is in low volume but we expect that it will increase significantly over the next few years.”
To pattern the RDL layers in advanced packages, the industry uses various lithographic systems. It’s challenging to pattern the finest RDL features in packages.
“Most advanced packaging lithography systems are designed for minimum features of 2µm or higher,” Flack said. “Going to smaller features requires exposing with a shorter wavelength and having a larger lens numerical aperture (NA). The major lithography challenges going forward for these advanced fan-out packages are: imaging sub-micron RDL with high-aspect ratios; minimizing overlay errors that occur from die shifting; extremely warped substrate handling; and support for very large 2.5D chip on wafer package sizes. Yield and productivity will drive the cost of adopting advanced fan-out packages. Only very high ASP devices can afford this kind of advanced packaging approach.”
In fan-out, die shift is one of the bigger problems. During the flow, the dies tend to move in the epoxy material, causing variation and other issues.
Brewer Science is working on an approach to solve the problem. The technology uses a thin film in a mold compound that works like a stencil.
Laminated polymetric die-stencil fill concept. Source: Brewer Science
“Die stencil is an alternative to using the traditional EMC fan-out approach. It doesn’t require the use of a typical EMC in order to create the constituted substrates. It is advantageous because it reduces the warpage commonly observed with EMC fan-out technology and is flexible in integrating all sorts of dies into the package, independent of their sizes and features,” Brewer’s Yess said.
So going forward, customers will have new and different advanced packaging options on the table. These technologies are impressive, at least on paper. But as before, it’s easier said than done to integrate them in systems, especially at the right price point for demanding customers.
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