SiC Growth For EVs Is Stressing Manufacturing

The electrification of vehicles is fueling demand for silicon carbide power ICs, but it also is creating challenges in finding and identifying defects in those chips.

Coinciding with this is a growing awareness about just how immature SiC technology is and how much work still needs to be done — and how quickly that has to happen. Automakers are pushing heavily into electric vehicles, and the transition from 400V to 800V battery systems is accelerating the transition from IGBT to SiC devices in EV power modules. The result will be an exponential growth in SiC demand, and all of it needs to work flawlessly.

“The power semiconductor market is undergoing significant change due to the rapid growth of electric vehicles (EVs) and renewable energies,” said Frank Heidemann, vice president and technology leader of SET at National Instruments. “This transformation drives the need for increased efficiency, particularly in the automotive sector, leading to the emergence of wide-bandgap technologies such as silicon carbide and gallium nitride.”

SiC devices possess several properties that make it a better choice than silicon-based IGBT devices.

“Power density, higher voltage, and attractive thermal properties are the three things that really make silicon carbide-powered devices attractive for people who are either making very efficient motor drivers, or very dense motor drivers or power conversion circuits,” said Jay Cameron, senior vice president of power ICs at Wolfspeed. “We’re seeing a lot of applications that need significant power, but in smaller and or lighter form factors. So if you’re looking for the ability to have lighter-weight systems that use less copper, with SiC you’ve got an opportunity to make a voltage-for-current tradeoff while still maintaining high power levels.”

Power electronics also help reduce weight, which impacts range in a vehicle, as well. SiC-based power modules require fewer ICs, and they don’t need to be cooled as much, which shrinks the number of required thermal solutions. Those modules perform a range of basic voltage conversions between the various battery systems, and between the charging stations and battery systems, and motors and battery systems.

IGBT devices have been the primary ICs supporting these functions in 400V battery systems. To reduce overall power module costs, engineers already had begun switching from IGBTs to SiC devices, but that shift is accelerating with the conversion from 400V to 800V battery vehicles. SiC can operate up to 1,200V.

Fig. 1: System diagram of a Mitsubushi iMiEV showing the locations of modules that use power ICs. Source Wikimedia Commons, Creative Commons license BY-SA 3.0

To meet the growing demand for SiC, the industry needs to ramp up production. That means addressing manufacturing challenges that have long slowed SiC production. Those challenges include high device costs, as well as defect and reliability concerns. To address costs, SiC substrate manufacturers are moving from 150mm to 200mm wafers. Yet this expected exponential growth poses challenges for screening SiC devices, which will require innovations from manufacturers and inspection and tester vendors.

“These wide-bandgap devices pose unique challenges in end-of-line (EoL, i.e., testing performed at end of a manufacturing process for wafers, packages, modules, systems) testing, as they exhibit different failure mechanisms and models compared to traditional silicon devices,” said NI’s Heidemann. “Moreover, testing them for reliability and high voltage environments, up to 2,000 volts or higher, presents a significant challenge for EoL test systems, which were not previously designed for such requirements.”

The manufacturing process for SiC sometimes results in defects that impact basic functionality and performance properties, necessitating screening with inspection and electrical test. High-voltage and high-current testing require carefully designed test systems that both provide the necessary current and voltage, as well as protect equipment when the inevitable short circuit occurs.

Until now, that screening has been done at low volume. Scaling up to higher volume requires innovations for screening to be effective and cost-effective.

Inspection and metrology methods
A key difference between silicon and SiC power ICs relates to the growth of the substrate. As a homogeneous crystalline structure, silicon has few sub-surface defects. In contrast, silicon carbide is grown via chemical vapor deposition, which can cause a wide range of sub-surface defects such as stacking faults and micro-pipes. During the subsequent epitaxial growth, crystalline faults can propagate. Also, because SiC is a brittle material, it’s more vulnerable to surface defects such as scratches and pits, which can affect the whole wafer.

In addition, SiC wafers are prone to breakage during the handling process, and sawing into die introduces more opportunities for cracks, which can propagate. Hence, inspection throughout wafer and assembly processes is essential.

Due to its high throughput, engineers primarily rely on optical inspection systems during SiC manufacturing. A number of companies offer specialized optical inspection tools for SiC that include review and classification capabilities.

Metrology is less straightforward. Metrology feedback involves a wide variety of parameters that process engineers need to measure, including substrate planarity and thickness, crystal lattice orientation, electrical resistance, and surface roughness. Those, in turn, require a diverse set of systems.

“White light interferometry (WLI) profilers are used at substrate manufacturer sites in quality assurance/quality control to measure wafer roughness (sub-nm) for Si, GaN and SiC,” said Sandra Bergmann, product manager for white light interferometers at Bruker. “SiC substrates are more challenging to produce. Polishing is difficult due to its hardness. Hence, WLI is critical to optimize/keep track of the polishing process.”

SiC devices can be planar or trench-based technologies. WLI is especially useful for trench depth metrology.

“For high-aspect ratio trench depth measurement during a high-voltage IC process, WLI can resolve from 2µm opening till 40µm depth,” said Bergmann. “It is non-destructive with parallel inspection of all trenches within the field of view. We usually use 5X objective with 0.5mm² interrogation field. We also provide full variation of depth along the trench across the field of view.”

Wafer inspection needs to consider both surface defects and sub-surface defects, the latter being particular import for SiC.

“Optical inspection techniques are used for defect inspection, while X-ray and photoluminescence are used for metrology,” said Burhan Ali, product marketing manager for inspection at Onto Innovation. “The challenge for optical inspection is that it is effective in finding surface defects at high throughput, but it quickly runs out of steam when it comes to sub-surface crystal defects. In those cases, the photoluminescence technique has proven fruitful to detect sub-surface crystal defects on SiC substrates and epitaxial layers.”

Inspection occurs throughout the assembly process. With high throughput and low equipment investment, optical is the preferred method. But optical is limited to surface defects. For detecting sub-surface defects in moderate to high density, X-ray is the preferred solution because it can be run in 2D at high speeds. Acoustic inspection, meanwhile, can easily detect delamination, but it requires the part to be immersed in water.

“Manual, optical, X-ray inspections are non-destructive methods,” said George Harris, vice president of global test services at Amkor Technology. “Basic X-ray inspections are useful for reviewing package integrity. A large fraction of systemic defect modes are easily identified with X-ray, and hence it is popular with customers. Destructive mechanical cross-sectioning of packaging and scanning electron microscopy may be performed at specialized failure analysis labs, per customer requests.”

Inspection is not limited to electrical issues. It also can be used to identify defects that can affect thermal management.

“In the packaging space, most electrical defects are associated with wires crossing/contacting the molding process and causing a short,” said Brad Perkins, product line director at Nordson Test & Inspection. “There is also the need to look at thermal protection, which is why engineers inspect the die attach, as that is part of the thermal management. Too large of a void, too high of a total percentage of voiding, or a large enough delamination will result in hot spots in the die that will result in a premature failure. As many of the power devices are used in high-reliability applications (automobiles, trains, windmills, etc.) the cost of failure can be very high, so inspecting for defects that would cause premature field failures is very cost-beneficial for the manufacturer.”

Fig. 2: X-ray for void inspection. Source Nordson Test & Inspection

Test methods
Volume production of SiC is relatively new, and so is its use in automotive applications. As a result, rigorous test processes are being devised to ensure quality and reliability. Testing is done at multiple temperatures, voltages and frequencies. This is essential because defects can appear benign at lower frequencies and voltages, but then manifest at higher frequencies and/or voltages.

Because of their analog nature, power ICs require functional and performance tests. For power ICs, tests are divided into static and dynamic tests, i.e., DC and AC. Static testing is done at room temperature, while dynamic testing is conducted at high temperatures.

“Static test is not a challenge anymore, because the device under test (DUT) is tested under steady state,” said Fabio Marino, managing director of Advantest Italy. “This means low power. Even if it is super-high voltage, it will be low current, and if it’s super high current it will be low voltage. The real the challenge the engineering community has is dynamic test. Dynamic test is extremely high power because it tests the DUT transition from ON to OFF state, and vice-a-versa. This means very high current at very high voltage. While the transition represents a very small amount of time, it is at extremely high power.”

Reliability concerns related to gate threshold drift observed in wide-bandgap devices also drive the rigorous testing.

“With regard to testing, qualification, and EoL, we need to perform more thorough testing and delve deeper into device characteristics. For example, gate drift, a phenomenon specific to wide-bandgap devices, varies significantly among different market players. Some exhibit dramatic drift over a car’s lifetime, while others show minimal drift,” noted NI’s Heidemann. “Interestingly, even within the same supplier, the behavior can differ from one device generation to another. Consequently, there is a greater need for comprehensive testing, including EoL and qualification, which is more demanding compared to the silicon world.”

Today, wafer test cells cannot run dynamic testing because the wafer chuck has a very high stray inductance. Engineers only use static tests at wafer sort. Even then, because of the high voltages being applied, there is a risk of sparking that can damage good devices.

“Since this is a physical challenge, it’s been handled the same way for years — through managing the air gap, and of course, managing the air,” said Tom Tran, product manager for power discretes at Teradyne. “As voltages start to climb toward 400V and beyond, generally we see a shift away from just using physical spacing to adding compressed dry air (CDA) through a pressure chamber that seats against the wafer.”

The current limitation of wafer test has prompted development of bare die testing.

“The power modules are the most robust package parts that we can test both static and dynamic,” said Advantest’s Marino. “But the drawback is those packages contain multiple switches — 6 up to 48. If one single switch is broken, then you trash the full package, and this is extremely expensive. That’s why customers move to an intermediate test for the substrate, such as prior to final assembly. So it’s a bit less expensive, but still you have the 6 up to 48 devices. The breakthrough innovation is to test bare die. This screens every single switch (static and dynamic tests). By only assembling good die, the customer can benefit in terms of cost of assembly.”

Fig. 3: Test insertions span wafer, die, package, and power module. Source: Advantest

Bare die testing carries a risk of damaging the probe card and/or ATE if a failing die sinks a high current. But engineers have figured out a way to address this.

“In moving to bare die, CREA (now part of Advantest) specifically developed a patented technology — probe card interface (PCI),” Marino said. “This is hardware and a software algorithm that detects abnormal current consumption. The probe card to test the bare die has 3,000 needles per die because each needle can only drive 1 amp. Between the tester and the probe card is the PCI, a hardware box. The PCI monitors the current flowing in each needle, or group of needles, in the probe card. In case of abnormal current distribution or current consumption (due to a failing part), the PCI immediately switches off the power. The part fails, but the chuck, the probe card, and the tester are protected.”

Fig. 4: Comparison between a test system with and without a probe card interface system. Source: Advantest

Once die have been assembled into a package, testing can screen for package-related defects and for defects that manifest during dynamic tests.

“Package-specific defect mechanisms are typically tested through a change in behavior from wafer to package-level testing, in addition to partial discharge testing,” said Teradyne’s Tran. “While partial discharge focuses more on the packaging and materials aspect, electrical test can reveal physical faults with the packaging process, such as continuity errors due to damaged wire bonding, or damage from the singulation process. Screening can also occur in the examination of mean shift and distribution from wafer sort to final package test.”

Reliability-related defects are very important to detect, and existing standards guide testing for both part qualification and production manufacturing.

“We employ various test methodologies for both end-of-line and qualification purposes,” said NI’s Heidemann. “In terms of qualification, industry standards like JEDEC and ECPE’s AQG324 define dynamic test scenarios specifically tailored to silicon carbide, to the introduction of a new material with distinct failure models. Therefore, qualification entails a considerable amount of dynamic testing, including dynamic H3TRB, DGS, and DRB tests, among others, which are relatively new compared to IGBTs. Similarly, in the end-of-line environment, a wide range of dynamic test scenarios is observed, varying from one customer to another. However, it can be stated that end-of-line testing extensively involves dynamic tests conducted under high-temperature and high-voltage environments. The goal is to ensure that these devices are dynamically tested to prevent the occurrence of failure effects throughout the production series.”

Future developments
To handle the demand for SiC devices, fabs are moving from 150 to 200mm wafers. For test and inspection processes to support the increased capacity industry, experts cite a number of innovations that could help. These range from changes to test systems to using analytics to better comprehend electrical impact of defects observed during inspection.

Innovation in test systems can shift screening capabilities earlier in the manufacturing flow and increase throughput. One such innovation would be a wafer chuck to enable dynamic testing on wafers. This requires reducing the chuck stray inductance from 600 microhenry to less than 100 nanohenry.

Currently, package test support is only for single-site testing. Test cells use a large handler that moves parts between several testers, with each tester running at specific temperatures and running either dynamic or static tests. Moving to multi-site testing would reduce overall cost. However, there’s a huge engineering challenge to run high energy tests in parallel. This requires innovation in ATE design.

An unexpected gap is availability of handlers, in particular for bare die.

“The big challenge comes from the handler side. We don’t have enough handler vendors or handlers in the market,” said Marino. “Handler companies announce more than one year lead time, while we operate with four months lead time. Thus, the market window is at risk. That’s why we are asking prober vendors to come into the game. Prober companies have the same core business — semiconductors. But automation companies have a big variety of industries to support, from watch assembly to semiconductors.”

Connecting data from various manufacturing steps in a consistent manner also can enable optimization of the manufacturing process and an understanding of defect impacts.

“With test stations devoted to specific sections of the complete test list, data integrity is important,” said Amkor’s Harris. “There has been a recent push to migrate the collected data on to the intranet cloud, where data analysis algorithms are continuously testing for workflow, test equipment, and systemic package and fabrication related fail mechanisms. Factory automation allows for closed-loop controls and results in yield improvement. Both optical and electronic technologies are used for unit level traceability.”

Such data connection will enable SiC manufacturing to accelerate yield learning and lower overall test costs.

“In general, compound semiconductor technology — be it SiC, GaN, GaAs, InP, or else — is where silicon was many years ago. It will likely take years of efforts and investments to get to low-cost defect-free 8-inch substrates. In the foreseeable future, substrate and epi-wafer quality will remain the problem in focus,” said Steve Zamek, director of product management at PDF Solutions. “Finding and identifying substrate defects is just the first step. Next comes aggregating all data types — defect inspection and review, inline metrology and electrical test data — in one platform. This is a non-trivial problem, as these data get acquired in geographically dispersed factories and tools. But once this is done, manufacturers are able to build predictive analytics models to maximize efficiency. Those that get there sooner will reap the benefits.”

Others agree that achieving traceability is non-trivial. With power ICs there is no electronic ID, so traceability is a challenge during assembly and test.

“In back-end devices that have a device ID, it’s possible to track,” noted Dieter Rathei, CEO of DR Yield. “But then you have a lot of devices where you lose the device-level traceability after the separation from the wafer. Then you see situations where devices are mixed up in batches. And unless you know which wafer has been put into which batch data correlation between wafer and package is not possible.”

Conclusion
The expected growth in EV production creates a challenge for engineering teams responsible for SiC IC production. The demand fuels changes from 150mm to 200mm wafer production, also stresses the current inspection and test processes. Many note that the SiC technology maturity is where silicon technology was three decades ago. As the technology matures to meet demand, engineering teams will need to address the defectivity with improved test systems and changes that reduce throughput times for both test and inspection processes.

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