7nm Fab Challenges

FinFET formation, mask challenges and back-end-of-line issues will make this node difficult and expensive.


Leading-edge foundry vendors have made the challenging transition from traditional planar processes into the finFET transistor era.

The first finFETs were based on the 22nm node, and now the industry is ramping up 16nm/14nm technologies. Going forward, the question is how far the finFET can be scaled.

In fact, 10nm finFETs from Samsung are expected to ramp by year’s end. The challenges for 10nm finFETs are basically known.

A 7nm finFET is expected to be an evolutionary extension of 16nm/14nm and 10nm finFETs. Chipmakers aren’t expected to make any radical changes with the structures or materials at 7nm.

Still, 7nm brings a new set of challenges. “Everything is getting harder,” said Mike Chudzik, senior director of the Transistor and Interconnect Group at Applied Materials. “Lithography costs, yield, performance and variability are issues. So, perhaps a better question is this—’What is not a fab challenge for 7nm?’”

One process, however, stands out among the rest at 7nm—lithography. In fact, foundries were originally counting on extreme ultraviolet (EUV) lithography for this node. But as it stands today, EUV won’t be ready for the early stages of 7nm, prompting the industry to make use of traditional 193nm immersion and multiple patterning.

“The biggest challenges and innovations will be in patterning,” said Matt Paggi, vice president of advanced technology development at GlobalFoundries. “You are going to see us pressing the lithography rules to the limits.”

And if that isn’t enough, there are other challenges at 7nm. “In addition to the challenges associated with multiple patterning—such as edge placement error, pitch walking and cost—interconnect RC delay is another significant issue limiting performance scaling,” said Yang Pan, chief technology officer for the Global Products Group at Lam Research. Foundry customers are beginning to get their arms around the design issues with 7nm. They will also need to get a handle on the manufacturing issues in order to have more realistic expectations about their design schedules.

To help the industry get ahead of the manufacturing curve, Semiconductor Engineering has taken a look at some of the more challenging process steps at 7nm. This includes mask making, patterning, transistor formation, interconnects and process control.

Nodes and cost

Before diving into the process steps, there are several issues surrounding 7nm. For one thing, it’s unclear what the term “7nm” means in the first place. To be sure, the definitions of both the 10nm and 7nm nodes are fuzzy, if not confusing.

And once foundries roll out 7nm, the specs might be all over the map. A hypothetical 7nm finFET is projected to have anywhere from a 12nm to 18nm gate length and a 45nm to 55nm gate pitch, according to IBM. In addition, 7nm could have a fin width of 6nm or 5nm, which is at or near the physical limit of a fin structure.

In comparison, Intel’s 14nm finFET technology has a 20nm gate length, analysts said. It has a gate pitch of 70nm.

In any case, there is one certainty about 7nm—it will be expensive to manufacture in the fab. Generally, 10nm and 7nm processes can be manufactured with nearly the same fab equipment. “7nm logic processes will probably require $160 million of fab equipment investment for every 1,000 wafers per month in terms of installed capacity,” said Samuel Wang, an analyst with Gartner. “This is a 60% increase from the 28nm.”

There are other variable manufacturing costs, including raw silicon wafers, labor and utilities. On top of that, the cycle times are also long at 7nm. “7nm logic can take more than 80 photo passes, if 193nm immersion and multiple patterning are used,” Wang said. “This compares to 50 passes for 28nm.”

In comparison, there are 66 mask steps at 16nm/14nm. “Based on these factors, you can see the complexity and the potential yield impact at 7nm,” he said.

Mask making
At 7nm, chipmakers hope to use two types of lithographic techniques in a complementary fashion—EUV and immersion/multi-patterning.

Today, though, the status of EUV is uncertain at 7nm. So initially, chipmakers plan to use 193nm immersion/multi-patterning. Then, if it’s ready, EUV will be inserted later for some layers. If it’s not ready, EUV will slip to 5nm.

As before, lithography determines the photomask type and specs. The photomask is a critical part of the flow. After the mask is made, it is shipped to the fab. The mask is placed in a lithography tool. Then, the tool projects light through the mask, which, in turn, patterns the images on a wafer.

Mask making is becoming more difficult at each node. For example, 193nm wavelength lithography hit its physical limit at 40nm half-pitch. To deal with the diffraction issues at advanced nodes, photomask makers must use various reticle enhancement techniques (RETs) on the mask.

One RET, called optical proximity correction (OPC), is used to modify the mask patterns to improve the printability on the wafer. OPC makes use of assist features, which are getting smaller and more complex at each node.

In addition, the number of masks per mask set is increasing at each node. At 16nm, for example, there are 60 masks per mask set, according to a survey from the eBeam Initiative. This figure is expected to jump to 77 at less than 11nm, according to the survey.

“Multiple patterning increases the number of total masks needed to manufacture a given chip,” said Aki Fujimura, chief executive of D2S. “This already puts pressure on the time it takes to manufacture each mask, but each of the mask patterns are also getting more complex. This is because each feature needs to be written more precisely.

“More aggressive OPC, like ILT (inverse lithography techniques) or shapes approaching ILT shapes, are needed to get the required process window,” Fujimura said. “This makes the mask shapes more complex and requires finer geometries and spacing for the mask.”

As a result, it will take a longer time to write or pattern the mask using today’s e-beam mask writers. This, in turn, equates to longer mask turnaround times and higher costs for customers.

“In addition, increased mask complexity and the need for geometries below 60nm require model-based processing to have enough precision,” Fujimura said. “Traditional fracturing is insufficient. With each addition of a corner into a given shape, and with each addition of a corner to corner distance that is less than 60nm-90nm, the gap between the drawn geometry and the actual mask image becomes significant. We believe that the computational advantage of GPU-acceleration makes accurate model-based processing possible for the 7nm node.”

Meanwhile, if the industry inserts EUV at 7nm, mask makers must contend with the complexities of EUV masks. For EUV, the sub‐resolution assist feature (SRAF) sizes on the mask range from 32nm to 40nm, compared to 60nm for optical. The SRAF 1x design sizes range from 8nm to 10nm for EUV, compared to 15nm for optical, according to Mentor Graphics.

All told, the write times for EUV masks are long. To reduce the write times, photomask makers want a new class of multi-beam mask writers. Still to be seen, however, is if these tools will be ready in time for 7nm.

Needless to say, the industry wants EUV at 7nm. But given the uncertain status of EUV, chipmakers are prepared to the meet the challenges with immersion/multi-patterning. “This will require more double and triple patterning schemes,” GlobalFoundries’ Paggi said. “You will see SADP and options like SAQP.”

What this means is more processing steps in the fab, thereby increasing manufacturing costs. “The number of mask layers is escalating, as we continue to use immersion lithography technology,” said Kelvin Low, senior director of foundry marketing at Samsung Semiconductor. “We have to do something else to bring the cost trajectory back to its normal curve.”

The answer, of course, is EUV. “The situation is we need EUV,” said Seong-Sue Kim, a technical staff member within the Semiconductor R&D Center at Samsung.

“The situation is we need EUV”

The deployment of EUV depends on the status of the power source, resists and mask infrastructure. “EUV is making huge progress,” said David Fried, chief technology officer at Coventor. “For example, you have the Pellicle, resist defectivity and other issues. Those things were dark clouds a few years ago. Now, the problems are clearly defined and there are competing solutions. People are working on them and those will be solved.”

Transistor formation
Chipmakers will likely extend the finFET to 7nm. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

Don’t expect any big changes in the material sets at 7nm, though. Chipmakers will have enough trouble scaling traditional silicon-based finFETs to 7nm. Take the contacted poly pitch (CPP) in a device, for example. Generally, a 14nm finFET has a 72nm CPP. At 7nm, chipmakers hope to scale the CPP to 36nm.

“There will be an evolution in material sets,” GlobalFoundries’ Paggi said. “The fundamental challenge that faces the industry is that you are shrinking the technologies. The spaces between the gates are obviously shrinking. We would call this CPP. That shrink is leaving less and less space for a contact between your gates.”

There are other issues. “The primary challenges will be contact resistance reduction and channel mobility improvement for better performance,” Lam’s Pan said. “We also need innovations to reduce parasitic capacitance.”

To extend the finFET, chipmakers will likely re-engineer the fin. One path is to make the fins taller. Taller fins provide more drive current, enabling faster chips at lower power, but they also increase device capacitance.

Taller fins provide more drive current, enabling faster chips at lower power, but they also increase device capacitance.

The most likely path is to scale the fin, which would reduce the capacitance. In one scenario at 7nm, both the fin pitch and height might be 30nm. In comparison, Intel’s 14nm finFET has a fin pitch and height of 42nm.

Meanwhile, for some time, the industry has been talking about new channel materials to boost the mobility in the device. As before, the next-generation channel material candidates are III-V, germanium (Ge) and silicon germanium (SiGe).

“There’s a ways to go before the end of silicon, and for truly scaled Ge or III-V devices that are competitive with silicon,” Applied’s Chudzik said. “So don’t expect exotic channel materials at 7nm. SiGe is one of the channel materials that is a viable dark horse contender. It’s not new and has been already used in planar devices. It offers major advantages for the PFET. But NFET is the device that needs the most attention.”

Patterning and other process steps are difficult. But what could undo Moore’s Law is arguably the most problematic part of device scaling—the backend-of-the-line (BEOL).

The BEOL is where the interconnects are formed within a device. Interconnects—the tiny wiring schemes in devices—are becoming more compact at each node, causing an unwanted resistance-capacitance (RC) delay in chips.

The average delay due to copper resistivity increased by 7.6% from 45nm to 22nm, according to a study from the Georgia Institute of Technology. But on average, the delay is expected to jump by 21.8% from 22nm to 11nm and by 48% from 11nm to 7nm, according to Georgia Tech.

There is no simple solution to the problem, however. “The interconnect is at an inflection point, and the form it takes will depend on pitch scaling as we move from the 20nm, 10nm and 7nm nodes,” said Mehul Naik, a principal member of the technical staff at Applied Materials. “Everybody scales differently, so the solutions to known interconnect high value problems such as metal fill, via and line R, capacitance scaling and reliability management are bucketed based on pitch, and not node. Pitch is the reference point now, not node.”

In any case, chipmakers will continue to face a number of challenges in the BEOL. This involves the traditional metallization scheme, usually known as the copper dual damascene process.

In a copper dual damascene structure, tantalum nitride (TaN) materials are used for the barrier. Starting at 20nm, cobalt (Co) replaced tantalum (Ta) for the liner. TaN and Co are expected to scale to 10nm and 7nm.

The industry is exploring new materials for the BEOL, and for good reason. “The problem at 7nm and below is that the barrier/liner thickness does not scale sufficiently, which leads to lower volume for copper fill and increased resistance,” Lam’s Pan said. “In addition, metal resistivity tends to increase at smaller dimensions due to surface scattering and/or grain boundary scattering. While we believe that copper will be extended to 7nm, the path for 5nm and beyond is less clear, and we are looking at solutions to further extend copper as well as the use of new materials.”

Another issue is low-k dielectrics. For years, the k-effective figure has been stuck at 2.4. Scaling low-k films is problematic, due, in part, to the poor mechanical properties of the materials.

“Low-k scaling is focused not so much on reducing film dielectric constant, but developing films with lower process induced damage to effectively get lower integrated capacitance for similar bulk film k,” Applied’s Naik said. “Effective k scaling continues to be driven by new materials with superior etch stop properties that enable thinning of dielectric etch-stop/barrier stack and reducing the fringe capacitance to lower effective k.”

Process control
Future devices will require structures with thin, precise and conformal films. And chipmakers will continue to grapple with structures that consist of only a finite number of atoms.

All told, chipmakers face an overlooked challenge–variation. “Variability control will determine how successfully we can continue power/performance/area scaling,” Lam’s Pan said. “We are entering the atomic-layer control regime, where every nanometer and every angstrom matters. Added to this, there is growing need for advanced process control capabilities to minimize variations, such as uniformity at the extreme edge of the wafer, surface stoichiometry, line-edge roughness, and intra-die uniformity for different feature sizes.”

Wafer inspection and metrology are also a critical part of process control. It is becoming more difficult and expensive to find killer defects at each node. And it’s harder to measure the structures in three dimensions.

In fact, there is no one tool that can handle all metrology needs for finFETs. “You will not be able to use a standard CD-SEM to measure the things you measured on it two generations ago,” Coventor’s Fried said. “You will need to move to scatterometry.”

AFM, CD-SEM, OCD and X-ray will all play a role in metrology at advanced nodes. “You will have to implement more complex and potentially more expensive hybrid solutions,” Fried said. In hybrid metrology, chipmakers use a mix-and-match of several different tool technologies and then combine the data from each.

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