Chip Industry Technical Paper Roundup: Oct. 28

Vertically integrated hybrid large area electronics platform; 3D-IC thermal simulation; photonics for sustainable AI; AI efficiency in data centers; inner gate length modulation of MFMIS NSFETs; column-based read disturbance in DRAM; microarchitectural defense against EM side-channel attack.

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New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Three-dimensional integrated hybrid complementary circuits for large-area electronics KAUST, Imperial College London, University of Manchester
DeepOHeat-v1: Efficient Operator Learning for Fast and Trustworthy Thermal Simulation and Optimization in 3D-IC Design Intel Corporation, University of California Santa Barbara, Cadence
Photonics for sustainable AI Boston University, NY CREATES, Lightmatter, Cornell Tech
Improving AI Efficiency in Data Centres by Power Dynamic Response University of Cambridge, Nyobolt Limited, Nanyang Technological University
Inner Gate Length Modulation of MFMIS Nanosheet FET Memory for Advanced Technology Nodes Samsung, Seoul National University
ColumnDisturb: Understanding Column-based Read Disturbance in Real DRAM Chips and Implications for Future Systems ETH Zurich, CISPA
ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors Northeastern University, Binghamton University

Find more semiconductor research papers here.



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