New Patterning Options Emerging

Several fab tool vendors are rolling out the next wave of self-aligned patterning technologies amid the shift toward new devices at 10/7nm and beyond.

Applied Materials, Lam Research and TEL are developing self-aligned technologies based on a variety of new approaches. The latest approach involves self-aligned patterning techniques with multi-color material schemes, which are designed for use in developing new finFETs and structures within the logic transistor itself. Others are developing new schemes for next-generation transistors and memory.

Used for the formation of logic and memory, self-aligned patterning techniques fall under the generic category of “patterning” in semiconductor manufacturing. Patterning is the art of developing tiny features and patterns on chips. Other technologies also fall under the broad “patterning” segment, such as extreme ultraviolet (EUV) lithography and optical lithography, among others.

Developed several years ago, self-aligned techniques utilize various process steps to ensure structures are aligned properly with each other. Generally, the new self-aligned technologies are split into two segments—multiple patterning, as well as self-aligned contacts/vias and other structures. Others use different names for the second segment. Imec calls it “scaling boosters,” while Applied refers to it as “placement” or “material-enabled scaling.”

In multiple patterning, the idea is to use a sequence of process steps in the fab to scale the feature sizes of a chip. The best-known examples are self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP).

Besides multiple patterning, chipmakers also use different self-aligned techniques to develop various structures, such as contacts and vias, within the transistor itself. The industry refers to these structures as self-aligned contacts and vias.

In one example, Intel recently introduced a 10nm finFET technology. Using a self-aligned technique, Intel incorporated a contact over active gate (COAG) structure within the finFET. Others are developing fully self-aligned vias and related structures.

These technologies are often overlooked, but they are becoming more critical. “Self-aligned structures like COAG are key to scaling,” said Mark Bohr, senior fellow and director of process architecture and integration at Intel. “Intel and others in our industry have applied self-aligned features in the past, such as self-aligned contacts and self-aligned vias, that have been needed to enable scaling.”

Self-aligned technologies use various process steps, such as deposition, etch and lithography, in the fab. Other schemes are more deposition/etch-centric with new material sets. It varies, depending on the device. And there are additional options in the patterning landscape, including direct-write e-beam, directed self-assembly, EUV, optical lithography and nanoimprint.

But to help the industry get ahead of the curve in self-aligned technologies, Semiconductor Engineering has taken a look at the trends for multi-patterning, contacts/vias and futuristic schemes.

Moving to multi-patterning
The process starts in a photomask facility. In the flow, a chipmaker designs an IC, which is then translated into a file format. Then, a photomask is developed based on that format.

A photomask is a master template for a given IC design. After the mask is developed, it is shipped to the fab and placed in a lithography scanner.

Then, a wafer is placed on a separate stage in the scanner. The wafer is coated with a light-sensitive material, called a photoresist. The scanner projects light through the mask, which patterns tiny images on a wafer.

For years, lithography was a straightforward process. A lithography scanner images the features on a wafer using a single exposure. It was more or less a single-patterning process. And for a long time, the industry believed that traditional optical lithography systems would last until 45nm node or so. In theory, the latest optical technology—193nm wavelength lithography—was supposed to reach its physical limit at an 80nm pitch, or 40nm half-pitch. Then, at 45nm, chipmakers were supposed to move to extreme ultraviolet (EUV) lithography. Using a 13.5nm wavelength, EUV patterns the features at the nanoscale.

That never happened. EUV was more complicated to develop than previously thought, and the technology has been delayed. Now, EUV is targeted for 7nm and/or 5nm. And because of the delays, the industry developed another solution, namely extending today’s 193nm wavelength lithography with multiple patterning.

It wasn’t easy moving from single- to multi-patterning. For years, the industry has used optical proximity correction (OPC) technology on the photomask. OPC makes use of tiny shapes, or sub-resolution assist features (SRAFs). The SRAFs are placed on the mask, which modifies the mask patterns to improve the printability on the wafer.

At 20nm, though, the SRAFs became too dense on the mask, making it more difficult to print discernible features on the wafer. And this is where multiple patterning fits in.

In multiple patterning, “the original mask shapes are divided between two or more masks, such that each shape has enough space around it to enable the OPC manipulations to make it printable,” explained said David Abercrombie, DFM program director at Mentor, a Siemens Business, in a blog. “Each mask is then printed separately, eventually imaging the entire set of originally-drawn shapes onto the wafer.”

Then, starting at 22nm/20nm, chipmakers implemented various multiple patterning schemes in the fab using a two-step approach. The first step is to pattern tiny lines on a wafer using 193nm lithography and multiple patterning. Then, the lines are cut into tiny and intricate patterns.

For the lines, the industry borrowed a technique used in the memory industry—SADP and SAQP. SADP/SAQP use one lithography step, plus additional deposition and etch steps, to define a spacer-like feature. Using SADP/SAQP, chipmakers can extend the device pitch beyond 40nm.

The big challenge is to cut these lines into tiny patterns. For this, some chipmakers use SADP and SAQP.

Others use double patterning, which reduces the pitch by 30%. This process uses two lithography and etch steps to define a single layer. This is also called litho-etch-litho-etch (LELE). Others use triple patterning, which require three exposures and etch steps (LELELE).

Fig. 1: Self-aligned spacer avoids mask misalignment. Source: Lam Research

Fig. 2: Double patterning increases density. Source: Lam Research

Multiple patterning extends IC scaling, but it also increases the complexity. For one thing, there are more process steps at each node, which translates into time and cost.

To make matters more difficult the device features become smaller at each node. On top of that, the features must be precise and placed on the exact locations on each layer of a device. A 28nm device has 40 to 50 masking layers. In comparison, a 14nm/10nm device has 60 layers, and that number is expected to rise to 80 to 85 layers at 7nm.

All told, the challenges escalate at each node, which increases the likelihood of errors cropping up in the process. “We can make smaller features by multiplying them. But placing them relative to each other, that is our fundamental roadblock. You are trying to overlay multiple layers to each other and they might have errors,” said Regina Freed, managing director of patterning technology at Applied Materials.

In patterning, the goal is to pattern tiny features in precise locations. If these are not precise and exact, that results in an unwanted misalignment, commonly called an edge placement error (EPE).

EPE is the difference between the intended and the printed features of an IC layout. If one or more EPE issues crop up in the production flow, the device is subject to shorts or poor yields.

EPE is represented by a numerical value. In simple terms, EPE is equal to the combination of various metrics–CD uniformity, overlay, line-edge roughness (LER) and variation.

Fig. 3: Multi-patterning process and EPE challenges. Source: Applied Materials

Some processes can easily meet the desired EPE numerical value or budget. But at times, the more difficult processes could exceed an EPE target level, which translates into poor yields.

Any solutions?
So for 10nm/7nm and beyond, what’s the best patterning solution? And which one will meet the EPE targets?

There is no single solution that meets all needs. As before, a chipmaker selects a given manufacturing technology, based on complexity, cost and other factors.

“There are multiple ways to get a pattern at a certain resolution,” Applied’s Freed said. “There will be a lot of different options. You can do SAQP. You can use EUV/double patterning. You can do EUV litho-etch-litho-etch. Each of the options has its own pros and cons. Customers will have a mix of them.”

EUV is one possibility, as it promises to reduce the number of process steps in the flow. DSA, multi-beam and nanoimprint are also possibilities.

Self-aligned schemes are another solution. These technologies work in conjunction with other fab tools to help align features. For example, EUV could be combined with an SADP/SAQP scheme for multi-patterning.

Generally, the industry has extended today’s self-aligned technologies to 10nm/7nm. But it is becoming challenging to use the conventional approaches. “As the industry moves into the advanced nodes, processing challenges related to size scaling become more and more critical,” said Eric Liu, senior process engineer at TEL, in a paper presented at the recent SPIE conference.

In the paper, TEL described a new SAQP approach to perform the line cuts for a 30nm pitch. “The most challenging pattern in the line-cut step is the single line-cut without defect formation,” Liu said. “At sub-7nm pitch, since the line pitch is as narrow as or more narrow than 30nm, (line-cut) is the most challenging process especially on single line (line-cut) process. There is a high risk that the device might suffer from limited yield and reliability.”

For this, TEL devised an SAQP technology using a multi-color material approach. (This is different than multi-color mask layouts used in multiple patterning.)

Traditionally, in SADP/SAQP, the flows involve various process steps and different materials. Generally, each material has the same color. The problem is that when using the traditional approach for line cuts in a 30nm pitch, TEL calculated the EPE budget exceeded the target value of 7.9nm. “The major technical problem of the (line-cut) process is edge placement error (EPE). EPE is defined as the sum of variations that induces placement error of blocking mask and process shift,” Liu said.

TEL’s new approach follows a standard SAQP flow with various lithography, deposition and etch steps. But in this approach, each material is assigned a different color based on the etch selectivity rate. For example, the process requires two lines with different materials. Each line is assigned a different color. Then, a blocking mask is assigned a different color.

Fig. 4: Step-by-Step multi-color process flow for 2L1C from lithography to spacer 3 deposition. Source: TEL

In simple terms, the colors serve as a guide in the flow, enabling more precise and accurate features. “If you make every other line in your long line/space pattern out of a different material, and those materials have different etch rates, it is possible to cut one line in an etch process without worrying whether the neighboring line is damaged by a misplaced cut pattern,” explained Chris Mack, CTO of Fractilia, in a blog.

Still, there are trade-offs with multi-color multi-patterning approaches in general. “We have built test structures as part of our R&D activities for logic applications,” said Richard Wise, technical managing director at Lam Research. “By building lines with different colors (materials), the subsequent randomly placed cut processes can be self-aligned to underlying lines using a selective etch process. This can effectively double or more the overlay margin for these cuts.”

But it adds more process steps and cost to the equation. “These solutions are only required if the overlay budget cannot be met using standard fab techniques and the tradeoff in complexity, cost, and design make economic sense,” Wise said. “Adoption in a product requires a tradeoff. Multi-color SAxP for self-alignment improves overlay at the expense of process complexity/cost and design flexibility. Design remains a challenge for broader adoption. At this point, the industry is focused on improvement to on-product overlay using other techniques that do not require these tradeoffs.”

All told, SADP/SAQP with multi-color techniques aren’t the only option on the table, but they do give customers choices.

Making contacts and vias
A leading-edge chip consists of three parts—the transistor, contacts and interconnects. Serving as a switch, the transistor consists of a source, gate and a drain.

The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another. Typically, a chip might have 10 to 15 levels of copper interconnects, which are connected using vias.

Connecting the transistor and interconnects is a sea of tiny contacts. Contacts are 3D-like structures with a small gap. The gap is filled with tungsten.

Fig. 5: Interconnect, contact and transistor at various nodes. Source: Applied Materials.

Until recently, chipmakers had few problems making contacts and vias. Take the contacts for example. In most chips, a gate resides between two contacts. At 90nm, the length from one contact to the other was about 200nm. By 22nm, though, the device scaled to a point where was little space for the contacts.

To solve the problem, chipmakers moved to self-aligned contact schemes. At 22nm, for example, Intel placed the contacts next to the gate. Using a self-aligned scheme, the metal gate is recessed. Then, a silicon nitride etch-stop layer is placed on top of the metal, according to Intel. The contacts are filled with tungsten.

In effect, self-aligned contacts enable a chipmaker to cram more structures on the device, a move that boosts overall area scaling.

At 10nm, Intel took it a step further. It placed the contact over the active gate (COAG). Using a different self-aligned process, Intel uses a silicon-carbide material as the etch-stop layer, according to a paper from Intel at IEDM. In addition, cobalt replaced the tungsten material to reduce the line resistance.

There are other examples, such as fully-aligned via processes. For years, the industry has made contacts and vias using damascene-like flows. In contacts and vias, you pattern holes on top of the surface using today’s 193nm immersion and multi-patterning. You drill a tiny hole with an etcher. Then, you line the hole and fill them with different materials.

At advanced nodes, chipmakers face several challenges making these self-aligned structures. For one thing, these structures have the same challenges as multi-patterning, such as EPE. Then, the contacts and vias are becoming smaller and harder to make at each node.

So to pattern the contact holes and vias, chipmakers hope to switch from 193nm lithography to EUV at 7nm/5nm. The other parts of the structure also require more complex manufacturing techniques. Contacts are good examples. “In the good old days, there was plenty of EPE margin,” said Uday Mitra, vice president of etch and patterning strategy at Applied Materials. “Now it’s no longer like a simple shrink. You are actually putting a contact over a gate. It’s like 3D scaling.”

COAG and fully self-aligned vias are complex, 3D-like modules inside the transistor itself. Many of these 3D-like structures lean more heavily on deposition, etch and new materials. “Basically, litho has been the main driver for scaling,” said Gaurav Gupta, research director for semiconductors and electronics at Gartner. “But with 3D devices, when you are trying to scale, it’s more than litho. Etch and deposition become important.”

To make these structures, vendors have developed a series of tools, materials and flows. “One way of doing self-aligned schemes is by using multiple materials, selective etch, selective removal and CMP,” Applied’s Mitra said. “You use the standard materials as much as possible.”

It also makes use of self-aligned technologies with multi-color material schemes. The flows and schemes depend on the device. “The whole world is moving this way. Materials-enabled processing is happening. It’s not just litho or EUV. With or without EUV, you need self-aligned schemes. You need materials-enabled patterning,” he said.

Applied Materials, for one, calls this “materials-enabled scaling.” Materials-enabled scaling isn’t exactly a new market, but it’s basically an evolution of the current self-aligned techniques. “You still have to use self-aligned structures. You need a combination of different materials. The sequence of process steps may vary. It’s a patterning problem being solved by materials, not by a classical litho shrink or overlay,” he said.

What’s next?
There is more to it, though. Applied and others are working on a futuristic technology called selective deposition. Using atomic layer deposition tools, selective deposition involves a process of depositing materials and films in exact places.

Selective deposition is still in R&D. Over time, these and other techniques promise to enable a wide range of futuristic devices. “For material-enabled scaling, new materials are projected to come into the picture for fabricating Ge/III-V, nanowires, graphene, VFET and TFET,” Gartner’s Gupta said.

Germanium (Ge) and III-V materials are targeted for the channels in next-generation transistors. Nanowires, vertical FETs (VFETs) and tunnel FETs (TFETs) are next-generation transistor types.

Clearly, self-aligned schemes will enable new devices and provide a much-needed boost for IC scaling. Without these and other innovations, Moore’s Law could possibly slow to a crawl.

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