Next-Gen 3D Chip/Packaging Race Begins

The first wave of chips is hitting the market using a technology called hybrid bonding, setting the stage for a new and competitive era of 3D-based chip products and advanced packages.

AMD is the first vendor to unveil chips using copper hybrid bonding, an advanced die-stacking technology that enables next-generation 3D-like devices and packages. Hybrid bonding stacks and connects chips using tiny copper-to-copper interconnects, providing higher density and bandwidth than existing chip-stacking interconnect schemes.

AMD is using hybrid bonding technology from TSMC, which recently updated its roadmap in the arena. Intel, Samsung and others are also developing hybrid bonding. And besides AMD, other chip customers are looking at the technology.

“TSMC says its technology will likely be adopted by all of their high-performance computing customers,” said Charles Shi, an analyst at Needham. “Hybrid bonding is also on everybody’s roadmap, or at least on everybody’s radar, in mobile applications.”

A relatively new process conducted in a semiconductor fab, copper hybrid bonding is an advanced chip stacking technology that promises to give chip customers some competitive advantages. To be sure, chip stacking isn’t new and has been used in designs for years. What’s new is that hybrid bonding enables near monolithic 3D designs.

Most chips don’t require hybrid bonding. For packaging, hybrid bonding is mainly relegated for high-end designs, because it’s an expensive technology that involves several manufacturing challenges. But it gives those chipmakers some new options, paving the way towards next-generation 3D designs, memory cubes or 3D DRAMs, and more advanced packages.

There are several ways to develop these types of products, including the chiplet model. For chiplets, a chipmaker may have a menu of modular dies in a library. Customers then can mix-and-match the chiplets and integrate them in an existing package type or new architecture. In one example of this methodology, AMD stacked two internally-developed chiplets — a processor and SRAM die — resulting in a 3D package that combines a high-performance MPU with cache memory on top. The dies are connected using hybrid bonding.

There are other ways to implement chiplets. Traditionally, to advance a design, vendors would develop a system-on-a-chip (SoC) and integrate more functions on the device at each generation. This chip scaling approach is becoming more difficult and expensive at each turn. While it remains an option for new designs, chiplets are emerging as an alternative for developing complex chips.

With chiplets, a large SoC is broken up into smaller dies or IP blocks, and re-aggregated into a completely new design. In theory, the chiplet approach accelerates time-to-market with lower costs. Hybrid bonding is one of many elements to enable the technology.

Fig. 1: AMD’s 3D V-Cache technology stacks the cache on a processor. Source: AMD

Packaging landscape
Chiplets are not a packaging type per se. They’re part of a methodology that includes heterogenous integration, where complex dies are assembled in an advanced package.

IC packaging itself is a complicated market. At last count, the semiconductor industry has developed around 1,000 package types. One way to segment the packaging market is by interconnect type, which includes wirebond, flip-chip, wafer-level packaging (WLP), and through-silicon vias (TSVs). Interconnects are used to connect one die to another in packages.

While there is a push to increase density in packages, many of these devices are still based on older technologies, such as wire bonding and flip-chip. In flip-chip, tiny copper bumps based on solder materials are formed on top of a chip. The device is then flipped and mounted on a separate die or board, so the bumps land on copper pads to form electrical connections. In flip-chip, the bump pitches on a chip range from 300μm to 50μm. A pitch refers to a given space between adjacent bumps on the die.

“We’re still seeing coarse-pitch packages at 140μm to 150μm. That’s still mainstream, and it’s not going to change anytime soon,” said Annette Teng, CTO of Promex, the parent company of QP Technologies.

WLP processes, meanwhile, are used to make fan-out packages, which started out as a relatively coarse technology. OSATs are now working to increase the density of fan-outs by shrinking the lines and spaces and by adding pillars and other 3D structures on top of them.

“(Fan-out) represents an important high-volume miniaturized package type for smartphones and other mobile applications,” said William Chen, a fellow at ASE. “We also have a vibrant area of innovation serving the areas of high-performance computing, AI, machine learning, and more.”

Meanwhile, 2.5D has become increasingly mainstream for high-performance applications, such as data centers, while true 3D packaging is just getting started. With 2.5D, dies are stacked or placed side-by-side on top of an interposer, which incorporates TSVs. The TSVs provide an electrical connection from the dies to the board.

Fig. 2: Examples of 2.5D packages, high-density fan-out (HDFO), packages with bridges, and chiplets. Source: Amkor

2.5D solves several problems. In many systems, a processor, DRAM and other devices are placed on a board. Data moves between a processor and DRAM, but at times this exchange causes latency and increased power consumption. In response, many high-end systems incorporate 2.5D packages with ASICs and HBMs. That allows the memory to be moved closer to the processing functions, enabling faster throughput.

Many of these packaging options can support chiplets, where dies are mixed and matched according to a chipmaker’s needs. “The system can be optimized by using the best processor components with an optimum performance/cost process node,” said Xiao Liu, senior program manager at Brewer Science.

Chiplets represent a paradigm shift. “This paradigm shift enables higher transistor densities at the package level versus the chip level, while also allowing a mix of devices, each separately fabricated at optimal nodes relative to their unique function, to be heterogeneously integrated into a common package for increased performance and reduced size, weight, and power. The future will be system-level integration and optimization,” said Brian Sapp, vice president and general manager at i3 Microsystems.

Using the chiplet approach, vendors have developed 3D-like architectures. For example, Intel recently introduced a 3D CPU platform. This combines a 10nm processor core with four 22nm processor cores in a package.

All high-end packages are seeing growth, driven by AI and other applications. “AI involves high-performance computing (HPC). We are seeing a lot of demand for flip-chip BGA, which is linked to AI or HPC applications. That also includes 2.5D, 3D, or high-density fan-out,” said Choon Lee, CTO at JCET.

Each of these packages uses one or more different manufacturing processes. What’s common among most advanced packages is the interconnect technology. In this case, it determines how you stack and bond the dies in a package.

Intel’s 3D CPU, HBM, and other chips use tiny copper microbumps as the interconnect schemes in the package, along with a flip-chip process. With HBM, tiny copper bumps are formed on each side of the DRAM dies. The bumps on those dies are then bonded together, sometimes using thermocompression bonding (TCB). In operation, a TCB system takes the dies, aligns them, and bonds the chips using force and heat.

Today, the most advanced microbumps involve a 40μm pitch, which equates to 20μm to 25μm bump sizes with 15μm spacing between the adjacent bumps on the die. In R&D, vendors are working on devices with bump pitches beyond 40μm. Here, customers have some options. First, they could develop chips using existing microbumps. Basically, solder-based microbumps extend from 40μm pitches today down to 10μm, where these schemes run out of steam.

“Managing small pieces of solder caps on tiny little solder bumps has its own distribution of available solder mass. And at some point, those aren’t going to be reliable,” said Mike Kelly, vice president of advanced packaging development and integration at Amkor. “Somewhere between 20μm and 10μm, customers will jump to the hybrid approach. It has a lot of advantages. The power between the die is low. The electrical signaling path is excellent.”

In hybrid bonding, the dies are connected using tiny copper-to-copper interconnects, not bumps. For packaging, the starting point for hybrid bonding is 10μm pitches and beyond.

Both microbumps and hybrid bonding are viable options. Customers can use one or the other in packages, depending on the application.

Why hybrid bonding?
Hybrid bonding isn’t new. For years, CMOS image sensor vendors have used it. To make an image sensor, a vendor processes two different wafers in a fab. The first wafer consists of a multitude of dies, each of which consists of a pixel array. The second wafer consists of signal processor dies.

Then, using hybrid bonding, wafers are bonded together with copper-to-copper interconnects at the μm-level. The dies on the wafer are then diced, forming image sensors.

This process is nearly the same for packaging. But for packaging, hybrid bonding involves a different set of assembly challenges, which is why it hasn’t moved into production until recently.

It holds great promise. Late last year, AMD introduced a server processor using hybrid bonding. Recently, AMD introduced the Ryzen 7 5800X3D, a high-end desktop processor. Using hybrid bonding, a 7nm SRAM is stacked and bonded on a 7nm processor. In effect, 64MB of L3 cache memory is stacked on the processor, tripling the memory density.

Then, in R&D, there are several developments in the arena. For example, using both microbumps and hybrid bonding, Imec has developed what it calls 3D-SoCs. In 3D-SoCs, you could stack any number of dies, such as memory on logic. For this, you co-design the memory and the logic die as a single SoC.

Hybrid bonding enables the most advanced interconnects in these devices. “To realize such 3D-SoC circuits, the 3D interconnect pitch needs to be scaled further beyond the current state-of-the-art. Our current research has demonstrated the feasibility of realizing such interconnections at 7µm pitch for die-to-die stacking and 700nm pitch for wafer-to-wafer,” said Eric Beyne, senior fellow, vice president of R&D and director of the 3D system integration program at Imec, in a paper at IEDM.

Nonetheless, AMD is using TSMC’s hybrid bonding technology, which is called SoIC. Compared to microbumps, TSMC’s technology provides more than 200X the connection density and 15X the interconnect density, according to AMD. “This enables a much more efficient and denser integration using less than one-third the energy per signal of competitive approaches,” said Lisa Su, president and CEO of AMD.

Meanwhile, in a presentation at the recent IEDM conference, Douglas Yu, vice president at TSMC, provided more details about the company’s SoIC roadmap. This outlines the hybrid bonding bump pitch scaling path for customers.

On the SoIC roadmap, TSMC starts with a bond pitch of 9μm, which is available today. Then, it plans to introduce a 6μm pitch, followed by 4.5μm and 3μm. In other words, the company hopes to introduce a new bond pitch every two years or so, providing a 70% scaling boost each generation.

There are several ways to implement SoIC. For example, AMD designed a 7nm-based processor and SRAM, which are manufactured by TSMC. Then, using SoIC, TSMC connected the dies with a 9μm bond pitch.

In theory, over time, you could develop various advanced chips, and bond them using TSMC’s technology at various pitches.

To be sure, the technology doesn’t replace traditional chip scaling. On the contrary, chip scaling continues. Both TSMC and Samsung are ramping their 5nm logic processes with 3nm and beyond in R&D.

At one time, the shift from one process node the next provided a significant boost in terms of power, performance, and area (PPA) for chips. At the most recent nodes, though, the PPA benefits are diminishing.

In many ways, hybrid bonding is one way to provide a boost in systems. “In the past, most of the PPA benefits are done by silicon. People used to let chip scaling drive system performance. But now, chip scaling as an engine is losing steam a bit,” Needham’s Shi said. “Eventually, you want to have hybrid bonding to lift the overall system-level PPA. If you want to be more technically precise, I would position SoIC as a powerful tool in the toolkit available to TSMC customers. SoIC is a great PPA booster for certain workloads.”

Intel, Samsung, and others have not released their hybrid bonding roadmaps.

Nonetheless, from an architectural point of view, all of this is not as simple as it may seem. Next-generation 3D packages might incorporate several complex chiplets at different nodes. Some dies could be stacked and bonded using hybrid bonding. Other dies will reside elsewhere in the package. So it will take a range of technologies to connect all of the pieces.

“Hybrid bonding may be required for those pushing the envelope to develop high-performance computing products,” said Richard Otte, president and CEO of Promex. “For 2D structures and applications, chiplets are likely to be interconnected utilizing high-density methods. These include interposers. 3D-ICs require stacking chiplets, and thus TSVs and copper pillars, as well as the 2D high-density interconnect processes.”

There are other challenges. In a package, all of the dies need to communicate with one another using die-to-die links and interfaces. Most of these die-to-die links are proprietary. There is a move to develop open standard links. “The biggest roadblock to chiplets becoming the new IP is standardization. Standard/common communication interfaces between chiplets must be established for this to be viable across multiple packaging providers,” Otte said.

Manufacturing challenges
On the manufacturing front, meanwhile, two types of assembly processes use hybrid bonding—wafer-to-wafer and die-to-wafer.

In wafer-to-wafer, chips are processed on two wafers in a fab. Then, a wafer bonder takes the two wafers and bonds them together. Finally, the stacked dies on the wafer are diced and tested.

Die-to-wafer is another option. Like wafer-to-wafer, chips are processed on wafers in a fab. The dies are diced from one wafer. Then, those dies are bonded onto a base wafer. Finally, the stacked dies on the wafer are diced and tested.

Fig. 3: Wafer-to-wafer flow. Source: Leti

Fig. 4: Die-to-wafer flow. Source: Leti

From the beginning, it’s important to have dies with good yields. Dies with sub-par yields could impact the performance of the final product. Therefore, it’s critical to have a good test strategy upfront.

“Some of the dies may have manufacturing defects that would ideally be screened out during test,” said Adel Elsherbini, senior principal engineer at Intel, during a presentation at IEDM. “However, if the test coverage is not 100%, some of these dies may pass as good dies. This is a particular challenge. Defective dies may result in lower final system yield, especially as the number of dies increase.”

Besides a good test strategy, a sound process flow is required. The hybrid bonding process takes place in a cleanroom within a semiconductor fab, not at a packaging house as with most package types.

It’s important to conduct this process in an ultra-clean cleanroom. Cleanrooms are classified by the cleanliness levels, which are based on the number and size of particles permitted per volume of air. Generally, semiconductor fabs incorporate cleanrooms with an ISO Class 5 or cleaner standard. In ISO Class 5, a cleanroom must have less than 3,520 particles at sizes of >0.5µm per cubic meter, according to American Cleanroom Systems. An ISO Class 5 cleanroom is equivalent to the older Class 100 standard.

In some cases, IC assembly at an OSAT is conducted in ISO 7 or class 10,000 cleanrooms or higher. This works for most package types, but not for hybrid bonding. In this process, tiny particles could invade the flow, causing device failures.

OSATs certainly could build facilities with ISO 5 cleanrooms, but this is an expensive endeavor. Hybrid bonding requires relatively expensive equipment. Plus, hybrid bonding involves several steps that are more familiar to semiconductor vendors.

In both the wafer-to-wafer and die-to-wafer flows, the process starts with a single damascene process in the fab. For this, a silicon dioxide layer is deposited on one side of the wafer. Then, a multitude of tiny vias are patterned on the surface. The patterns are etched, creating a multitude of tiny μm-sized vias on the wafer.

Copper materials then are deposited over the entire structure. The surface is planarized using a chemical-mechanical-polishing (CMP) system. This tool polishes a surface using mechanical forces.

The CMP process removes the copper materials and polishes the surface. What remains is copper metallization material in the tiny vias.

The entire process is repeated several times. Eventually, the wafer has a handful of layers. Each layer has tiny copper vias, which connect to one another in the adjoining layers. The top layer consists of larger copper structures, called bond pads. Dielectric materials surround the tiny bond pads.

Nonetheless, the damascene process, especially CMP, are challenging. It requires precise control across the surface of the wafer. “[On the wafer], the dielectric surface needs to be: (1) extremely smooth to ensure strong attraction forces when attaching the dies; and (2) very low topography to avoid voids or unnecessary stresses in the dielectric pre-bonding,” Elsherbini said in a paper at IEDM.

During these processes, though, several problems could occur. The wafers tend to sag or bow. Then, during the CMP process, the tool could over-polished the surface. The copper pad recesses become too large. Some pads may not join during the bonding process. If under-polished, copper residue can create electrical shorts.

In hybrid bonding, standard CMP processes may not do the trick. “This requires special CMP processing to control the ratio of chemical to mechanical etching as well as the number of CMP steps to maintain the planarity of the dielectric surface,” Elsherbini said.

After CMP, the wafers undergo a metrology step. A metrology tool measures and characterizes the surface topography.

“The major process challenges of copper hybrid bonding include surface defect control to prevent voids, wafer-level thickness and shape metrology along with nanometer-level surface profile control to support robust hybrid bond pad contact, and controlling the alignment of copper pads on the top and bottom die,” said Stephen Hiebert, senior director of marketing at KLA.

More steps
Following the metrology step, the wafers undergo a cleaning and an anneal process. The anneal step activates the dies.

From here, the process can go in two directions—wafer-to-wafer or die-to-wafer. In wafer-to-wafer, you have already processed the first wafer (A). Then, a second wafer (B) with dies undergoes the same process (damascene, CMP, metrology).

Then, the two wafers (A, B) are bonded using hybrid bonding. The chips are diced on the wafer and tested. The resulting stacked devices resemble 3D-like structures.

In die-to-wafer, meanwhile, a chipmaker would take the first wafer and activate the dies. Then, the chips on the wafer (A) are diced and tested.

Then, a second wafer (B) undergoes a damascene process, followed by CMP and a metrology step. That wafer is not diced and remains intact. Using a bonder, the dies from the processed wafer (A) are stacked and bonded on the base wafer (B).

The chips are then diced on the stacked wafer and tested. This in turn creates 3D-like devices.

For both wafer-to-wafer and die-to-wafer, vendors can use the same wafer bonder system. Several vendors sell these systems for hybrid bonding with nanometer-level placement accuracy.

In operation, the dies are placed on a table unit inside the wafer bonder. The processed wafer is placed on a separate wafer table in the bonder. Dies from the table are picked up, aligned and placed on the processed wafer.

At this point, the bond pads of the two structures are bonded using a two-step process—it’s a dielectric-to-dielectric bond, followed by a metal-to-metal connection. “Direct hybrid bonding refers to molecular bonding of two surfaces composed of copper interconnections within an SiO2 matrix,” explained Emilie Bourjot, a 3D integration project manager at Leti. “When these two surfaces are intimately in contact at room temperature, Van der Waals bonds create adhesion. Those bonds are then changed into covalent and metallic bonds after a thermal budget.”

The bonding process is challenging. “The first item to consider is placement accuracy and throughput. We need to support extremely fine pitch. We need to be able to place the dies very accurately,” Intel’s Elsherbini said. “This is achieved through design optimizations to make sure that the alignment fiducials have very good visibility and contrast, while not consuming too much of the die active area.”

The bonder can perform these tasks, but the challenge is to prevent unwanted particles and surface defects in the flow. A tiny particle can cause voids in the bond pads. If even a 100nm particle invades the bond pads, it can result in hundreds of failed connections.

Conclusion
Hybrid bonding is a complex but enabling process. It enables a new class of chips and packages.

AMD is first to utilize this approach, but others soon will follow. The race has just begun.

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