New approaches aim for better performance, more flexibility — and for some, lower cost.
Packaging houses are readying their next-generation advanced IC packages, paving the way toward new and innovative system-level chip designs.
These packages include new versions of 2.5D/3D technologies, chiplets, fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers and panels. One is combining fan-out with silicon bridges.
It’s a confusing landscape with a plethora of buzzwords and too many options. Nonetheless, some new technologies are ramping up, while others are still in the lab. Some will never make it out of the lab due to technical and cost reasons.
Advanced packaging isn’t new. For years, the industry has been assembling complex dies in a package. In just one example, a vendor will integrate an ASIC and a DRAM stack in an advanced package, which boosts the memory bandwidth in systems. Generally, though, these and other advanced packages are mainly used for higher-end, niche-oriented applications due to cost.
Recently, though, the industry has been looking at advanced packaging as a more mainstream option for chip designs. Traditionally, to advance a design, the industry develops an ASIC or system-on-a-chip (SoC). For this, you shrink different functions at each node and pack them onto a monolithic die. But this approach is becoming more complex and expensive at each node. While some will continue to follow this path, many are looking for alternatives like advanced packaging.
What’s different is that vendors are developing new and more capable packages. In some cases, these advanced packages even mimic a traditional SoC with lower costs. Some calls these “virtual SoCs.”
“For many years, the industry’s primary path for increased functionality and performance has been node scaling based on SoC integration,” said Eelco Bergman, senior director of sales and business development at ASE. “Now, with the industry moving beyond 16nm/14nm, we are starting to see more interest in die disaggregation, whether it’s for yield and cost reasons, functional optimization reasons, or IP re-use reasons. IC partitioning fuels the need for heterogeneous integration. However, rather than this integration taking place at the SoC level, it’s now being driven by packaging technology and its ability to create virtual SoCs out of disparate pieces of silicon.”
Meanwhile, at the recent IEEE Electronic Components and Technology Conference (ECTC), as well as other events, packaging houses, R&D organizations and universities presented a slew of papers, providing a sneak peak of what’s next in advanced packaging. They include:
Generally, these are more traditional package types. Many of these enable so-called chiplets. Chiplets aren’t a packaging type, per se. Instead, they are part of a multi-tile architecture. With chiplets, a chipmaker may have a menu of modular dies, or chiplets, in a library. Customers can mix-and-match the chiplets and connect them using a die-to-die interconnect scheme. Chiplets could reside in an existing package type or a new architecture.
Making fan-outs
IC packaging is an important part of the semiconductor process. Basically, after a chipmaker processes a wafer in a fab, the dies on the wafer are diced and integrated in a package. A package encapsulates the chip, preventing it from being damaged. It also provides electrical connections from the device to the board.
There are a plethora of package types in the market and each one is geared for a specific application. One way to segment the packaging market is by interconnect type, which includes wirebond, flip-chip, wafer-level packaging (WLP) and through-silicon vias (TSVs). Interconnects are used to connect one die to another one. TSVs have the highest I/O counts, followed by WLP, flip-chip and wirebond.
Fig. 1: Package technology vs. application. Source: ASE
Some 75% to 80% of today’s packages are based on wire bonding, which is an older technology, according to TechSearch. Developed in the 1950s, a wire bonder stitches one chip to another chip or substrate using tiny wires. Wire bonding is used for low-cost legacy packages, mid-range packages and memory die stacking.
Flip-chip is another popular interconnect used for a number of package types. In flip-chip, a sea of tiny copper bumps are formed on top of a chip using various equipment. The device is flipped and mounted on a separate die or board. The bumps land on copper pads, forming an electrical connection.
WLP, meanwhile, packages the dies while in a wafer-like format. The two main types of WLP packages are chip-scale packages (CSP) and fan-out. CSP is sometimes known as fan-in.
Fan-in and fan-out packages are used in consumer, industrial and mobile applications. Fan-out is considered an advanced package. In one example of fan-out, a DRAM die is stacked on top of a logic chip in the package.
“Advanced packaging is a broad suite of technologies that enables us to shrink the package,” said Cliff McCold, a research scientist at Veeco, in a presentation at ECTC. “(Wafer-level packaging) enables us to make smaller two-dimensional connections that redistribute the output of the silicon die to a greater area, enabling higher I/O density, higher bandwidth and higher performance for modern devices. A disadvantage of wafer-level packaging is that it is more costly than wire bonding. But importantly, it enables smaller packages and smaller devices that are critical for modern mobile devices like smartphones.”
Generally, in the fan-out flow, a wafer is processed in a fab. The chips on the wafer are diced and placed in a wafer-like structure, which is filled with an epoxy mold compound. This is called a reconstituted wafer.
Then, using lithography and other equipment, the redistribution layers (RDLs) are formed within the compound. RDLs are the copper metal connection lines or traces that electrically connect one part of the package to another. RDLs are measured by line and space, which refer to the width and pitch of a metal trace.
There are several challenges with fan-out. During the flow, the wafer-like structure is prone to warpage. Then, when the dies are embedded in the compound, they tend to move, causing an unwanted effect called die shift. This impacts the yield.
At ECTC, Onto Innovation presented a paper on a technology that could mitigate die shift. Onto described a site-by-site magnification and theta correction method by adjusting the reticle chuck position in a lithography stepper. Potentially, the technology could correct magnification errors up to +/- 400ppm, and theta errors up to +/- 1.65mrad.
There are other issues. Finer RDL lines and spaces reduce the CDs for the interconnections or vias in the layers. So in the flow, a lithography tool must pattern smaller vias, which presents some CD challenges.
To address these issues, Veeco and Imec presented a paper at ECTC about relaxing the CDs of the vias and creating elongated vias. “This design change significantly improves the intensity distribution at the wafer aerial image for the via, which increases the effective process window,” Veeco’s McCold said.
For this, researchers used Veeco’s stepper with a lens supporting 0.16 to 0.22 numerical apertures (NAs). The system supports i-line, gh-line or ghi-line wavelengths. For this study, researchers used i-line (365nm) and 0.22 NA.
More fan-outs
Nonetheless, fan-out is gaining steam. Amkor, ASE, JCET, Nepes and TSMC sell fan-out packages. There are different versions of fan-out. But in all cases, fan-out eliminates the need for an interposer used in 2.5D/3D technologies. As a result, fan-out is supposedly less expensive.
Fan-out is split into two camps—standard density and high density. Targeted for cell phones and other products, standard-density fan-out incorporates less than 500 I/Os. High-density fan-out has more than 500 I/Os.
The original fan-out technology is called embedded wafer-level ball-grid array (eWLB). ASE, JCET and others sell standard-density eWLB packages, although this market is somewhat static.
In a paper at ECTC, JCET and MediaTek are breathing new life into eWLB by presenting details about a technology called FOMIP (Fan-out MediaTek Innovation Package). Basically, FOMIP appears to be a finer pitch eWLB package on a substrate. The first FOMIP appeared in 2018, although work is underway to develop a next-generation version.
The technology follows a traditional fan-out flow, which is referred to as a chip-first process. Also using a flip-chip process, FOMIP consists of a 60μm die pad pitch and 1 RDL layer with 5μm lines and 5μm spaces.
“It is believed that FOMIP technology can be further applied to a much finer die pad design with an advanced silicon node, such as a 40μm die pad pitch with 2μm/2μm LW/LS design,” said Ming-Che Hsieh, an application engineer at JCET, in a presentation at ECTC. Others contributed to the work.
Meanwhile, vendors continue to develop new high-density fan-out packages. At ECTC, for example, ASE described more details about a chip-last version of its hybrid fan-out package. This package, called Fan Out Chip on Substrate (FoCoS), can accommodate 8 complex dies with an I/O count of <4,000. It supports 3 RDL layers with ≦2µm/2µm line/space.
ASE offers FoCoS in a traditional chip-first process. In a chip-last flow, the RDLs are developed first, followed by the other process steps. Both chip-first and chip-last are viable and used for different apps. “Fan-out chip-last increases yield, and allows the fabrication of fine-line RDLs; therefore, it can utilize more I/O for high-end applications,” said Paul Yang, who works in the R&D center at ASE, in a paper. Others contributed to the work.
ASE also described some of the manufacturing issues with chip-last fan-out and how to address them. As stated, wafer warpage is problematic and impacts yield. In some cases, the thickness and coefficient of thermal expansion (CTE) of the glass carrier are among the issues that cause warpage.
To gain an insight into wafer warpage, ASE used a metrology technology with three-dimensional finite element analysis. ASE used digital image correlation (DIC), which a non-contact measuring technique that uses multiple cameras. DIC evaluates displacement and strain on surfaces and maps the coordinates. Using simulations and DIC, ASE is able to find the optimum range of the glass carrier thickness and CTE to improve warpage.
Meanwhile, at ECTC, SPIL, part of ASE, presented a paper on Fan-Out Embedded Bridge (FOEB) technology for chiplets. Used for multi-chip packages, FOEB is less expensive than 2.5D. “FOEB is an integrated chiplet package that could integrate heterogenous dies, such as GPUs and HBMs, or homogenous integrated devices,” said C. Key Chung, a researcher from SPIL, in a presentation at ECTC.
A bridge is a tiny piece of silicon that connects one die to another in a package. The most notable example here is Intel, which has developed a silicon bridge technology called Embedded Multi-die Interconnect Bridge (EMIB).
Unlike EMIB, which is a die-to-die connection, SPIL’s bridges are embedded in the RDL layers to connect dies. Regardless, bridges are positioned as an alternative to 2.5D packages using interposers.
SPIL has developed a test vehicle for FEOB. The vehicle integrates an ASIC die and 4 high-bandwidth memory (HBM) dies. The ASIC is in the middle of the package with two HBMs on each side.
Four bridges are embedded in the RDL layers. In total, there are three RDL layers. Two are 10μm/10μm for power and ground, while one is 2μm/2μm for the signal layer. “This chiplet package enables near monolithic short-reach connections between dies. FOEB can have multiple RDL layers and silicon bridges that have much finer line/space for interconnections,” Chung said.
Fan-out is moving in other directions. In a paper at ECTC, Amkor described a new RDL-first fan-out process with chip-to-wafer bonding. Then, in another paper, A*STAR described a fan-out antenna-in-package for 5G.
Moving from 2.5D to 3D
At the high-end, the industry traditionally uses 2.5D. In 2.5D, dies are stacked on top of an interposer, which incorporates TSVs. The interposer acts as the bridge between the chips and a board, which provides more I/Os and bandwidth.
In one example, a vendor could incorporate an FPGA or ASIC with HBM. In HBM, DRAM dies are stacked on top of each other. For example, Samsung’s latest HBM2E technology stacks eight 10nm-class 16-gigabit DRAM dies on each other. The dies are connected using 40,000 TSVs, enabling data transfer speeds of 3.2Gbps.
2.5D brings the logic closer to the memory, enabling more bandwidth in systems. “Traditionally, the interest (for interposers) has been in high-end graphics,” said Walter Ng, vice president of business development at UMC. “Now, we are seeing more interest in performance enterprise solutions. We’re also seeing interest in non-traditional areas.”
But 2.5D is expensive and relegated to high-end applications, such as AI, networking and servers. So the industry is looking for solutions beyond 2.5D. High-density fan-out is one option. This has fewer I/Os than 2.5D, although it is closing the gap.
3D-ICs present another option. A 3D-IC involves a multi-die architecture using active interposers and/or TSVs. The idea is to stack logic on memory or logic on logic in a 3D package. GlobalFoundries, Intel, Samsung, TSMC and UMC are developing various forms of 3D technologies.
3D architectures can be integrated with chiplets. This is where you mix-and-match dies or chiplets with different process nodes in a package. “We are just in the early stages of the chiplet approach,” said Ramune Nagisetty, director of process and product integration at Intel. “In the coming years, we will see it expand in 2.5D and 3D types of implementations. We will see it expand into logic and memory stacking and logic and logic stacking.”
Today, the industry is developing or shipping 2.5D/3D packages using existing interconnect schemes. The dies are stacked and connected using an interconnect technology called copper microbumps and pillars. Bumps and pillars provide small, fast electrical connections between different devices.
The most advanced microbumps/pillars are tiny structures with a 40μm pitch. Using existing equipment, the industry can scale the bump pitch possibly at or near 20μm. Then, the industry needs a new technique, namely copper hybrid bonding.
In copper hybrid bonding, chips or wafers are bonded using a dielectric-to-dielectric bond, followed by a metal-to-metal connection. This is a challenging process. Defects are among the biggest issues.
TSMC, meanwhile, is working on a technology called System on Integrated Chip (SoIC). Using hybrid bonding, TSMC’s SoIC technology enables 3D-like architectures. “An SoIC integrated chip not just looks like (an SoC), but it behaves like an SoC in every aspect in terms of electrical and mechanical integrity,” said C. H. Tung, a researcher from TSMC.
At ECTC, TSMC presented a paper on an ultra-high density version of SoIC. This version enables 3D multi-tier chip stacking, creating what TSMC calls Immersion-in-Memory Computing (ImMC). In one example of ImMC, a device could have three tiers. Each tier has logic and memory dies. The tiers are connected using hybrid bonding.
Meanwhile, GlobalFoundries is also working on hybrid wafer bonding, enabling fine-pitch 3D architectures. It has demonstrated face-to-face die stacking with 5.76μm pitches. “Future stacks will observe finer pitches at less than 2μm and different terminal surface designs,” said Daniel Fisher, principal packaging engineer at GlobalFoundries.
Not all of the action is in hybrid bonding. At ECTC, Brewer Science described a permanent bonding material with low moisture absorption and high thermal stability. The materials are used for advanced wafer bonding applications.
“In the present work, a new permanent adhesive bonding material is introduced for MEMS, 3D integrated circuit and wafer-level packaging applications,” said Xiao Liu, a senior research chemist at Brewer Science, in a presentation.
In Brewer’s bonding flow, a material is spin-coated on a wafer. The wafer is baked. A separate carrier wafer is placed on the wafer and cured at low temperatures. The two wafers are then bonded.
More packaging
Meanwhile, AI startup Cerebras recently made headlines when it introduced a technology using wafer-scale integration. It’s a wafer-level device with more than 1.2 trillion transistors.
At ECTC, TSMC demonstrated a wafer-scale system integration package based on its fan-out technology, called InFO. The technology is called InFO_SoW (System-on-Wafer). “InFO_SoW eliminates the use of a substrate and PCB by serving as the carrier itself,” said Shu-Rong Chun, the lead author in a paper from TSMC.
MIT, meanwhile, described 200mm wafer-scale superconducting multi-chip modules (S-MCM). This is used for interconnecting multiple active superconducting chips for next-generation cryogenic processing systems.
Conclusion
Not all solutions will require wafer-scale packaging. But clearly, customers are beginning to take a harder look at advanced packaging.
There are more innovations than ever in packaging. The challenge is to find the right package at the best price point.
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Well described an overall activities of advanced packages
SkyWater/DARPA 3DSoC deserves a mention, as it has seemingly been manufactured. Hopefully we learn more about it this year and it isn’t delayed too much by COVID.
Great article. Another noteworthy ECTC 2020 publication is by Samsung on its ISC (Integrated Stack Capacitor), which is essentially a much improved DTC (Deep Trench Capacitor), which, is a 3D vertical capacitor formed by etching a deep trench (hence the term “DT”) into the RDL or IC substrate.
is there 8um pitch packaging ?
lets say 7umX7um pad and 1um space
thanks