Chip Industry Technical Paper Roundup: June 30

Processing-using-DRAM interference; atomic-scale plasma processing; gallium oxide phase instability; event-driven reinforcement learning for fab control; microarchitectural timing leaks in embedded processors; LLM-assisted RTL generation; TPU training supercomputers.

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New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems 🔗 The University of Tokyo, ETH Zurich, CISPA, RIKEN
Recent Progress in Atomic-Scale Controlled Plasma Processing 🔗 Nagoya University, Boise State University, Korea Institute of Fusion Energy, Hitachi High-Tech Corp., Princeton Plasma Physics Laboratory
Coordination-Sensitive Nanoscale Analysis of Defect-Driven Phase Transformation in Si-Doped Gallium Oxide 🔗 University at Buffalo, The Ohio State University, Lawrence Livermore National Laboratory
Event-Driven Reinforcement Learning Enables Long-Horizon Control in Semiconductor Fabrication 🔗 Politecnico di Milano, STMicroelectronics
MIPSBLEED: Uncovering Microarchitectural Timing Leaks in Pervasive Embedded Processors 🔗 Rochester Institute of Technology
LLM4RTL: Tool-Assisted LLM for RTL Generation 🔗 UC Riverside, Futurewei
Google’s Training Supercomputers from TPU v2 to Ironwood: Architectural Stability, Scale, Resilience, Power Efficiency, and Sustainability Across Five Generations 🔗 Google, UC Berkeley

Find more semiconductor research papers here.

 



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