Concerns about security and supply chain availability prompt new push.
The United States is taking the first steps toward bringing larger-scale IC packaging production capabilities back to the U.S. as supply chain concerns and trade tensions grow.
The U.S. is among the leaders in developing packages, especially new and advanced forms of the technology that promise to shake up the semiconductor landscape. And while the U.S. has several packaging vendors, North American’s share of global packaging production stands at only 3%, according to a new report from the IPC trade group and TechSearch International. A large percentage of packaging production is concentrated in Asia, leaving the U.S. in a precarious position as advanced packaging grows in importance across the semiconductor industry, according to the report.
All told, the U.S. lacks larger-scale packaging production capabilities, substrates, and wafer bumping services, according to the report. Amkor, Intel and other U.S. companies are addressing these issues, but there are some challenges here.
Indeed, this remains a non-trivial effort with a lot of moving parts. In the semiconductor production flow, chips are manufactured in one location, and then encapsulated in a package in a different facility in Asia, Europe or the U.S. The chipmaker decides where a chip is manufactured and packaged.
While the U.S. is a leader in chip design, it has seen a decline in new fabs and capacity. A large percentage of fab capacity is concentrated in Asia. While that trend continues from a pure volume standpoint, Intel, Samsung, TSMC and others are building new fabs in the U.S. Clearly, chip manufacturing is critical for maintaining technological leadership, both from a supply chain and economic perspective, as well as for security reasons.
The same is becoming true for packaging. Newer forms of advanced packaging are becoming a viable alternative to develop complex chip designs, making this technology a strategic asset for many. Over the years, the U.S. defense community has been the main proponent of wanting various onshore fab and packaging capabilities for security reasons. Now, there appears to be demand for more packaging capabilities from a broader range of customers.
“Semiconductor packaging is an integral part of the semiconductor supply chain,” said Kevin Engel, vice president of the FlipChip/Wafer Services Business unit at Amkor. “There is interest across our U.S. customer base to not only increase front-end semiconductor fabrication in the U.S., but to add wafer-based processing like copper pillar bumping, packaging and test.”
For this, U.S. vendors are directing their resources towards all packaging types, especially advanced packaging. But for either case, there’s a problem. Years ago, the U.S. shifted a large percentage of its packaging production to Asia. “The United States has more than 25 outsourced semiconductor assembly and test (OSAT) companies, many with impressive capabilities. However, U.S. OSATs lack capacity to meet increased demand,” said Jan Vardaman, president of TechSearch, and Matt Kelly, chief technologist of IPC, in a recent report.
For high-volume manufacturing, IC vendors rely on OSATs with massive factories in Asia. Some chipmakers have their own in-house packaging plants in Asia and elsewhere. That won’t change anytime soon, and customers will continue to engage with the OSATs in Asia and elsewhere for a long time.
But the global semiconductor industry is changing, causing many to take a harder look at the supply chain. During Covid-19, for example, chip shortages have been rampant across several sectors. Capacity is also tight at the foundries and OSATs in Asia, prompting many to realize that the U.S. is too reliant on offshore manufacturing. To make matters worse, the U.S.-China trade war is compounding tensions in the region, where most of the leading process technology is located. Any disruption would have a major impact on U.S. access to leading-edge processes and packaging technology.
So the U.S. needs to strengthen its position in fab capacity as well as packaging. “Failing to strengthen U.S. advanced packaging capabilities while boosting production of chips will lengthen the existing semiconductor supply chain, as manufacturers will be forced to send their chips abroad for packaging and assembly,” said Vardaman and Kelly.
There are several efforts to bring back or re-shore large-scale packaging in the U.S., but it will take time and money. Plus, OSATs work on razor-thin margins. So developing a successful business model with competitive labor rates are among the challenges here.
Nonetheless, here are some of the activities taking place in the U.S.:
Packaging landscape
In the early days of the semiconductor industry, packaging was simple, and many North American chipmakers had their own onshore assembly/packaging operations.
Back then, packaging was a labor-intensive process using manual equipment. So starting in the 1970s, many North American chipmakers moved their packaging/assembly operations to lower-cost labor sites throughout Asia.
At the time, several OSATs emerged in Asia, providing low-cost assembly/packaging services to outside customers. Then, many multinational chipmakers began to divest their packaging operations, selling them to the OSATs.
Intel, TI and others kept their internal packaging plants in Asia and elsewhere. Some realized that packaging was a differentiator in product design.
That’s especially true today. At one time, packages were bulky and took up space. Over time, vendors developed innovative and sleek packages, enabling dies with smaller form factors and better performance.
And over the years, vendors have developed various advanced package types, which are making inroads in systems. “Advanced packaging has become integral to embedding increased functionality into a variety of electronics, such as cellular phones and self-driving vehicles, by supporting high-device density in a small footprint,” said Sandy Wen, a process integration engineer at Coventor, a Lam Research Company.
Packaging is becoming important in other ways, too. Traditionally, to advance a chip design, you would integrate more functions on an ASIC every generation. This is becoming more challenging at each turn, especially below 28nm.
“It has become more and more difficult for foundries and integrated device manufacturers (IDMs) to scale to the next technology node without a significant increase on the cost of ownership due to the tremendous investments,” said Xiao Liu, senior program manager at Brewer Science, in a paper.
While the ASIC method is still an option for new designs, many are looking for alternatives, such as advanced packaging. Chiplets are the next big things here. For this, a chipmaker may have a menu of modular dies in a library, allowing customers to mix-and-match the chiplets and integrate them into a new chip architecture. Chiplet-like architectures can mimic an ASIC, but they can be developed at lower costs, and presumably more quickly.
But all forms of packaging are important for chip designs, including everything from commodity-level to advanced packaging. The problem is that a large percentage of all packages are manufactured in Asia, and the associated ecosystem is there, as well. In 2019, China had the most packaging facilities (114), followed by Taiwan (106), the rest of Asia-Pacific (65), North America (35), Japan (27), Europe (19) and others, according to Stephen Rothrock, CEO of ATREG, in a recent presentation.
This is why the U.S. is looking to bolster its capabilities. Today, U.S.-based OSATs are capable of providing various technologies, such as wirebond, flip-chip and advanced packaging. They just need larger-scale production capabilities, but not in all areas.
“The most likely increased volume enablement in the U.S. will be devices built with leading-edge, newer technologies,” said Richard Otte, CEO of Promex, the parent company of QP Technologies. “This includes photonics, wafer-level and chiplet assembly, rather than re-establishing manufacturing capacity for established packages, such as DIPs, BGAs and QFN.”
Where the gaps are
Today, there are about 1,000 package types in the market. One way to segment the packaging market is by interconnect type, which includes wirebond, flip-chip, wafer-level packaging (WLP), and through-silicon vias (TSVs). Interconnects are used to connect one die to another in packages. TSVs have the highest I/O counts, followed by WLP, flip-chip, and wirebond.
Some 75% to 80% of today’s packages are based on wire bonding, according to TechSearch. Wire bonding mainly has been used for low-cost legacy packages, midrange packages, and memory die stacking.
It makes no sense to build larger-scale wirebonding capacity in the U.S. Today, U.S.-based OSATs provide wirebonding services, with large-scale wirebonding conducted in Asia.
Flip-chip is another story. This technology is used to develop ball-grid array (BGA) and other packages, which are found in smartphones and other products. The flip-chip manufacturing process is conducted by an IDM, foundry, or OSAT. In this process, copper bumps or pillars are formed on top of a chip. The device is then flipped and mounted on a separate die or board, so the bumps land on copper pads to form electrical connections.
The U.S. has some flip-chip wafer bumping technology, but it needs more capabilities. In total, Taiwan accounts for 40% of the world’s bumping capacity, followed by Korea (27%), China (16%), North America (6.5%) and others, according to IPC and TechSearch.
Flip-chip and other packages consist of several components, such as a base material or substrate. In total, the U.S. fabricates only 1.3% of all substrates for packaging, while the rest comes from Asia, according to the firms.
It’s a mixed picture in advanced packaging. Consider fan-out WLP, for example. In one example of fan-out, a DRAM die is stacked on a logic chip. In 2020, TSMC was the leader in fan-out with 66.9% share, followed by Taiwan’s ASE (20%), China’s JCET (5.1%), U.S-based Amkor (3%) and others, according to Yole Développement.
Meanwhile, TSVs are used in advanced 2.5D/3D packages, which are aimed at high-end systems. In 2.5D/3D, dies are stacked or placed side-by-side on top of an interposer, which incorporates TSVs.
“TSVs are the enabling technology of 3D-ICs, as they provide electrical connections between the stacked chips. The main advantage of the 3D-IC technology with TSVs is that it provides much shorter interconnections between different components,” said Luke Hu, a researcher at UMC, in a recent paper.
Samsung, TSMC and UMC are the main suppliers of interposers, according to IPC and TechSearch. In North America, GlobalFoundries, Micross, NHanced and SkyWater offer interposers.
Fig. 1: Different options for high-performance compute packaging, interposer-based 2.5D vs. Fan-Out Chip on Substrate (FOCoS). Source: ASE
The situation is better with chiplets, the next big battleground in packaging. AMD, Intel, and Marvell are pursuing this approach. AMD is relying on TSMC, while Intel has its own, in-house capabilities.
Who’s doing what
Several types of companies produce packages. For example, IDMs are chipmakers with their own fabs. Some but not all IDMs have their own packaging operations, which mainly produce packages for their own chips.
Foundries make chips for others, and some provide packaging services. OSATs provide third-party packaging/test services. And some system houses have various foundry and packaging operations.
Both Samsung and TSMC plan to build new and advanced fabs in the U.S. in 2024, but they have no plans to add a packaging plant to the mix. Intel is an IDM that recently re-entered the foundry business. Intel also has its own, internal packaging operations in Asia, Central America and the U.S.
Intel took a step into the merchant packaging market in 2020, when the U.S. Department of Defense (DoD) awarded the company a contract in its State-of-the-Art Heterogeneous Integration Prototype (SHIP) program. In the SHIP program, U.S. government agencies have access to Intel’s packaging/chiplet capabilities in the U.S.
Then, in early 2021, Intel announced plans that it would transform its existing New Mexico facility into an advanced packaging manufacturing center. Intel will invest $3.5 billion in the facility, which will develop packages for its internal products as well as for foundry customers.
Intel already has developed chiplet-like products, with others in R&D. “[Intel’s packaging technology] allows us to mix and match compute tiles to deliver the best products,” said Keyvan Esfarjani, senior vice president and general manager at Intel.
The U.S. defense community is a major customer for Intel and others. This segment has been a proponent of onshore chip and packaging manufacturing. This is one way to prevent adversaries from tampering or counterfeiting a chip product. The defense community will go offshore if it can’t find a domestic source.
Recently, though, onshore packaging has gained interest beyond the defense community. “It started to show up in the narrative inside of the DoD, where there’s a desire to have packaging onshore. This is to ensure that the chips that DoD purchases are not tampered with and are readily available in case of supply chain disruptions,” said Brad Ferguson, senior vice president and general manager of SkyWater Florida. “It’s not just DoD, though. There is a strong pull from our commercial customers to bring this onshore. When I say this, I’m blending standard packaging and advanced packaging into the same narrative. That said, it all has to be competitive.”
SkyWater Florida is the new packaging unit of SkyWater, a U.S.-based foundry vendor. In its Florida facility, SkyWater is developing packaging capabilities in several areas, including:
SkyWater is rolling out these technologies in phases, and sees a place for more packaging capabilities in the U.S. It hopes to take a page from one business model. “The fabless model hinges on ready access to capacity to meet your needs, whether that’s in Asia, Europe or the U.S. The fabless model relies on the flow of materials uninterrupted through the supply chain. It is a very successful model supported by foundries and OSATs,” Ferguson said. “Here’s the heart of the question-Is there is a play for the U.S. to re-shore the OSAT model and make a go of it? I would argue that advanced packaging is our entry point to re-shore that function in the U.S.”
Meanwhile, several U.S. defense contractors provide foundry and/or packaging services. Many are part of the DoD’s Trusted Foundry program, which provides secure onshore manufacturing services to the defense community.
One defense contractor, Northrop Grumman, recently announced plans to open a new packaging facility in Florida. The facility, called the Micro-Line (μ-Line), will consist of various backend wafer post-processing capabilities, including passivation, solder bumping, dicing, advanced inspection and test for up to 300mm wafers.
Slated to open in early-2022, the μ-Line has the capability to serve Northrop Grumman and external customers. “Northrop Grumman has existing microelectronics packaging capabilities, but the μ-Line is a first of its kind back-end wafer post-processing facility, enabling vertical integration from foundry to packaging,” said Scott Crudele, vice president of navigation targeting and survivability operations at Northrop Grumman. “The μ-Line gives Northrop Grumman an in-house packaging source that is tailored to meet defense customer performance, reliability, affordability and quality requirements.”
U.S. OSATs also are expanding. In total, there are dozens of OSATs of all sizes. ASE is the largest, followed by Amkor, China’s JCET, Taiwan’s Powertech, and China’s Tongfu, according to IPC and TechSearch.
Fig. 2: Another view of OSAT rankings. Source: TrendForce.
For years, a large percentage of manufacturing capacity among the OSATs has been located in Asia. That won’t change anytime soon. In fact, many OSATs continue to expand their manufacturing operations in Asia to meet booming demand in the market.
“[In 2021], we doubled our CapEx for wirebonding,” said Joseph Tung, CFO at ASE, in a recent conference call. “And [in 2022], the pattern will be shifting somewhat more to advanced packaging as well as test.”
Meanwhile, JCET recently opened the second phase of its packaging and testing facility in China’s Jiangsu Province. “JCET has achieved record results in recent years and has entered a steady growth trajectory,” said Li Zheng, CEO of JCET. “These operations will play an important role in fueling the group’s long-term development.”
Amkor also is expanding in Asia. The company is the largest U.S.-based OSAT, although it does not have a manufacturing base in the U.S.
That could change. Amkor has stated its intentions to build a packaging plant in the U.S. Amkor’s decision depends, in part, on whether the U.S. government ratifies the so-called CHIPS For America Act, a $52 billion plan to boost U.S. chip manufacturing.
That’s only one piece of the puzzle, though. The U.S. also needs to develop an ecosystem to support large-scale packaging, such as materials and substrates, as well as a skilled labor force.
“We are optimistic that government movement on the CHIPS act along with other incentives can bring packaging volume production to the U.S.,” Amkor’s Engel said. “Materials, including substrates, is another important aspect to building a more complete ecosystem into the U.S. Labor costs and skilled worker availability become more challenging as we go further down the supply chain. Packaging and some material lines require a high labor content, which increases the cost gap to Asia. These are areas where we are working with local organizations and universities to identify solutions.”
Promex’s Otte pointed out that the U.S. can leverage some of its existing organizations to solve some of these issues. For example, in 2015, the U.S. established AIM Photonics, which provides the fabrication, packaging, and testing of silicon photonics. Meanwhile, NextFlex, a U.S.-based group that develops flexible electronics, is another example.
“We need to be creative and use these facilities to build next-generation prototypes, and develop U.S. sources for materials and parts,” Otte said. “Also, of significant value is the continuing buildup of engineering talent to support these efforts.”
Promex is one of many U.S. OSATs that are expanding their onshore footprints. QP Technologies moved to a new and larger facility in California. QP also is ramping up a substrate design and fabrication service.
Meanwhile, Draper, an engineering services firm, has been selected for two U.S. DoD contracts totaling $14 million. i3 Microsystems, a U.S.-based OSAT, is the sub-contractor in the project. The goal is to bring up volume production of advanced packaging for defense systems.
“There are now many demonstrated examples containing clear technical, cost, and performance advantages that can be derived from using packaging. Systems-in-package designs could be seen as the first generation of this thinking,” said Justin Borski, director of business development and programs at i3. “Today, the volume production of these examples is dominated by overseas production. But with the continuation of semiconductors into the single-digit nanometer nodes, the inclusion of an advanced packaging solution in a system over the course of the next 10 to 20 years will become the norm to achieve a heterogenous design efficiency. Therefore, some production onshoring back to the United States is critically strategic for the semiconductor companies based in the U.S., particularly in support of the Department of Defense.”
Another U.S.-based OSAT, NHanced Semiconductors, is also expanding. The company provides various advanced packaging services, such as chiplets, 2.5D/3D and other technologies. “It is just as important to onshore these technologies as it is to have wafer fabs onshore. It is a matter of national security in and of itself,” said NHanced President Bob Patti.
Conclusion
Clearly, packaging is critical. The new and advanced forms of the technology are becoming even more important.
The U.S. has all the pieces in place. It just needs more of them to boost its packaging capabilities. “Both standard packaging and advanced packaging are needed in the U.S.,” Patti said. “It is true that the cost structure of onshore standard packaging will complicate a re-shoring effort. For instance, I’m not sure I have a good answer as to how to long-term economically support high-volume manufacturing of flip-chip. Advanced packaging is closer to a silicon foundry business and it is easier to see a long-term financial model that works in this space. Regardless, the U.S. needs to onshore a significant amount of the advanced packaging and a large slice of the more standard packaging.”
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