Optical methods need to comply with increasing warpage, finer RDL pitch, and trace size.
Key Takeaways:
Soaring AI/HPC device demand is driving leading-edge foundries to support the transition from wafers to panels to accommodate increasingly larger device sizes. But to ensure that panels with multiple redistribution layers are known-good, inspection equipment must cope with shrinking RDL features, smaller bump pitch, and the warpage that comes with panels’ larger form factors.
Once primarily relegated to small chips, panel-level packaging has become increasingly attractive for AI/HPC device makers as package size grows to 80 x 80mm and beyond. While the thermal management associated with high energy consumption has been a prevailing concern, the insatiable need for more compute power in a single package has reached an area limit. Silicon interposer-based packages are generally limited to 100 x 100mm, the largest size at which yield, lithography, warpage, and cost are reasonable. But with panel-level packaging, form factors will range from 310 x 310 mm to 600×600 mm, which TSMC has said will complement CoWoS, not replace it, in some very large packages.
However, meeting the interconnect density requirements of high-density fan-out (HDFO) pushes panel manufacturers into new territory.
“It represents a challenge for PLP manufacturers due to large package sizes, the integration of multiple chiplets or devices in the same package, and more interconnect density enabled by lower pitches, smaller RDL L/S, and more RDL layer count,” said Gabriela Pereira, senior technology and market analyst for semiconductor packaging at Yole Group.
Fan-out panel-level packaging typically uses a chip-last manufacturing process; hence, the need for inspection to assure known-good panels. To support HDFO, layer count goes from 3 to 9, and trace and bump pitches decrease from 20 to 5 microns. In addition, several industry experts said that manufacturers are targeting 2 micron pitches within the next 5 years.
“For panel-level packaging, the first thing is that the manufacturing requirements have become more stringent. The smallest feature size becomes more like the front-end (i.e., wafer processing). This drives more inspection,” said Monita Pau, senior director of product marketing at Onto Innovation. “If you look at panel level packaging you’re committing known good dies onto a package, in either an interposer or a substrate. You better make sure that these are defect-free before you commit a very expensive KGD onto the package.”
Engineering teams rely upon metrology, inspection, and electrical test to develop and maintain a panel manufacturing process with sufficient yield and quality. Early and frequent measurement provides the data to detect process drift, process anomalies, and defects. That, in turn, enables tweaks to process development and material properties, as well as prompt response to yield and quality excursions during production.
On the positive side, engineers have a broad set of measurement tools at their disposal. Optical inspection remains the primary method, but non-optical solutions may soon be needed.
“Existing advanced packaging metrology and inspection tool platforms are largely built around existing optical inspection and optical metrology platforms, adapted for panel formats,” said Yole’s Pereira. “The main techniques in use are optical AOI, optical 2D/3D, confocal, interferometry, profiler-based metrology, warpage and bow metrology tools, overlay and CD optical inspection, visual and optical carrier inspection for glass panels or glass carriers. Leading suppliers such as KLA and Onto Innovation leverage cross-platform architectures that can be adapted to PLP and advanced IC substrates with minimal modifications, while some vendors have developed PLP-dedicated tools.”
Still, the shift to HDFO panels does demand more from the inspection and metrology equipment.
“This migration brings wafer/fab class requirements onto formats that were historically inspected with PCB-grade sensitivity,” said Arun Aiyer, CEO and CTO of Avarustech. “These requirements include sub-2µm RDL line/space, sub-20µm bump pitch, sub-micron overlay, hybrid-bond-ready surfaces, transparent-substrate handling, and through-glass via (TGV) characterization. At the same time, panel-size standardization, warpage control, and equipment readiness remain unresolved. These changes tighten process windows and amplify mechanical distortion. Inspection and metrology must therefore move from a discrete quality gate to a core enabler of manufacturability.”
Measuring x,y and z for RDL and bumps
Multiple industry experts note that achieving high yield remains difficult for HDFO panels. Metrology and inspection provide essential data to yield and quality engineers. To support AI/HPC device designs, the layer count increases, and trace pitch and bump/pillar pitch decrease, but micropillar height increases. Inspection and metrology steps must be added at every layer, and the measurement resolution must increase with decreased feature size.
Miniaturization stresses the optical systems for both resolution and the ensuing throughput time per panel.
“When you have smaller objects, your optics resolution should also get smaller than the size of the object you are going to inspect. Currently, the minimum RDL line width is 5 microns in mass production, with future projections to shrink to 2 microns,” said JD Shin, director of customer success at Koh Young Technology. “For easier calculation, let’s choose the current line-width of 5 micrometers and a future line width of 1 micrometers. This means your resolution needs to be 5 times smaller than the conventional resolution. If you halve the resolution with the same type of camera, your inspection speed will be slower by four times.”
This increase in throughput time directly corresponds to the camera’s field of view, pixel count, and the requirement for improved resolution. The tradeoff between measurement sensitivity and the speed of measurement is typically addressed with faster physical scanning and the associated calculations. But it’s also a data management challenge. To put this in perspective, consider that the inspection of a 600 mm panel with 1 micron resolution results in ~1012 pixels per layer.
“It’s always sensitivity versus throughput,” said Onto’s Pau. “Either you have high sensitivity and lower throughput, or you have high throughput but lower sensitivity. Usually you try to balance these two aspects, because you want to make sure you are not missing killer defects. But on the other hand, you don’t want to go super slow.”
Vias connect the RDL layers. As the number of layers increases, the via stack-up grows, but the via area decreases. The mechanical stresses inherent in material properties, smaller vias, and the manufacturing process affect via formation. AOI is limited in evaluating the via quality.
“The RDL layers are becoming complicated from 3 layers up to 9 layers,” said Kyoung Rok Park, corporate vice president of research and development at Amkor Technology. “That has an impact on the stacking, i.e., the vias between layers. Even if we perform inspection at every single layer with AOI, how do you know about the stacking?”
Park noted that today electrical test is used to screen via defects. However, earlier detection methods provide more timely data for engineers to correct processing, as well as screening for known-good panels. That, in turn, opens the door for other modalities such as infrared and X-ray.
As bumps/micropillars’ pitch decreases and aspect ratio increases, traditional 2D inspection becomes insufficient because bump/micropillar quality affects the bonding yield and quality. With multiple camera angles, optical measurement equipment can create 3D images, and the resulting richer data can provide additional insight.
“Three-dimensional measurement/inspection becomes more critical than in the past when you had bigger bump sizes,” noted Koh Young’s Shin. “If you have smaller sizes, making the perfect bump of the same size is much more challenging. That is the reason why inspection is needed in 3D. Our equipment can provide this type of measurement, including the bump height and volume.”
Fig. 1: 3D measurement of solder bump. Source: Koy Young Technology
In the bumps/micropillar lithography process, photoresist thickness is an important parameter. Before the panel is exposed, irregularities in the photoresist can be detected and reworked through removal and redeposition. But that requires measuring thick films (hundreds of microns) at nanometer resolution, and this combination of specs is a challenge for traditional optical measurement techniques.
“You lose yield if bumps or micropillars are not coplanar. As the 3D stacking gets higher, and as the dimension of the die gets larger, you’re putting more components on the micropillars. Yet as the pillar height gets taller your planarity requirements remain the same. This makes it more difficult to manufacture,” said Chris Claypool, senior director of R&D for FilmTek product line at Bruker. “There are metrology tools that measure the coplanarity after the bumps and pillars are formed. We measure further up the line in the lithography stage, where they’re measuring the resist thickness and the resist uniformity. Because you can reprocess at that step. Normally with ellipsometry or reflectometry, you’re not going to be able to measure anything thicker than 30 microns.”
Bruker has an optical design that enables measuring up to 2,000 microns of dielectric thickness. “That’s unnecessary for front-end applications, but in packaging, particularly for bump and pillar planarity, it’s critical to have nanometer resolution for very thick films,” Claypool said. “What we’re seeing is in the packaging the thicknesses originally were in the 50 to 100 micron range for the bumps. Now the last generation was up to 450 microns, and the next generation we’re working on now is going to be up to 650 microns.”
Coping with warpage
As panel area increases engineers worry about the effect that warpage has on manufacturing processes. This includes the metrology and inspection methods which provide vital feedback on the RDL trace pitch, contamination defects, missing or excess metal on vias or micropillars, etc. Thus, optical measurement systems, the primary spectrum of choice, need to deliver good-quality measurements despite warpage.
“The biggest challenges are concentrated around scale, flatness, alignment, and process variability,” said Yole’s Pereira. “Process uniformity becomes harder because temperature, pressure, and material properties can vary across a much larger area. Warpage control is one of the most critical challenges, creating handling instability, die shift, photolithography alignment errors, yield loss, reliability issues, and electrical performance degradation. Hence, there is a need to adapt existing AOI, optical metrology, warpage metrology, profiler, interferometry, and 3D inspection platforms to larger panels. Equipment suppliers are scaling field of view, stage handling, data processing, warpage measurement, and automation so that wafer-level methods can work on larger panel formats.”
For optical measurement systems, the field of view and focal depth influence resolution and throughput. Warpage can affect optical focus, and consequently the measurement.
“Another challenge is that if you have finer resolution, from optical point of perspective the focal depth becomes more critical,” said Shin. “If you have small resolution, you have much narrower focal depths. So even with very small warpage, the image that you receive can be very blurry.”
Handling of panels can mitigate warpage.
“One of the biggest challenges with panel-level packaging is that you’re dealing with a much larger size than a wafer. The handling differs from a wafer form factor,” said Onto’s Pau. “Even though we do wafer-level packaging, you can imagine the panel surface area is much bigger. It’s always struggling with warpage. How are you going to hold the panel so that you can still do inspection?”
Others also stress the requirements on panel handling and focus capability that warpage mitigation requires.
“The first challenge you face is the warpage. How to you handle the warped panel, i.e., how do you suck it down and make it flatter? Because if you want the throughput, you need your system to quickly travel from one point to another,” said Samuel Lesko, senior director general manager of TSOM Business Unit at Bruker. “But with optical instruments, you have a certain working distance for focus. So you have to be careful to flatten out a full panel and avoid any collision with the instrumentation. The second challenge is with throughput. You need to have a reference base, such that the auto-focus time is minimal. So either you find a way to suck down the panel, or you find a way to get fast auto-focus. Or, you combine both techniques. And this choice is also a function of the panel/substrate material.”
However, the increased manufacturing process complexity results in a set of defects that are not visible to optics.
“The central challenge is that panel packaging combines wafer-class feature sizes with PCB-class mechanical instability. This stresses resolution, throughput, and stability in ways that existing tools were not designed to handle. Large panels deform, warp, shrink, expand, and locally shift far less predictably than wafers,” observed Avarustech’s Aiyer. “FOPLP (fan-out panel-level packaging) shows significantly higher warpage than equivalent FOWLP (fan-out wafer-level packaging) because CTE-induced warpage scales with dimension. Differential thermal expansion between polymers, metals, and silicon dies can induce severe bow and die shift during curing and debonding. As a result, critical defects are no longer purely visual. They are coupled to substrate distortion, residual stress, RDL deformation, coplanarity, and buried-interface behavior. A panel can pass conventional AOI and still fail because local height, overlay, or stress signatures were not measured in context.”
Conclusion
AI/HPC devices are expected to shift to HDFO panel-level packaging. But the transition is not as simple as adopting wafer-level techniques known to achieve high-density RDL over to a panel substrate. As RDL layers increase and pitch and size decreases, inspection and metrology become even more important in factories than ever before.
Optical inspection and metrology equipment (AOI) continues to be the most common wavelength used by engineers for RDL panel manufacturing. But the combination of specs and panel form-factor challenges its detection ability due to mechanical instability that accompanies panel materials and size. In other words, warpage complicates every aspect of optical measurement techniques.
“Panel-level packaging inspection and metrology is at an inflection point. Legacy PCB and substrate AOI are being pushed to their limits. At the same time, semiconductor-grade metrology has only been partially adapted to the scale, materials, and mechanical instability of large rectangular substrates up to roughly 600 × 600mm,” noted Avarushtech’s Aiyer. “The major shift is that inspection is no longer only a pass/fail step. It is becoming the data engine for adaptive lithography, where offline die-shift metrology feeds ML algorithms that drive global, zonal, per-die, or site-by-site overlay correction. Still, the industry lacks a single high-throughput, closed-loop, panel-native platform that can correlate visual defects, dimensional errors, and process-induced deformation in one coordinate frame across the full panel.”
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