Although IC packaging industry braces for slower growth in 2019, advanced packaging remains a bright spot.
The IC packaging industry is bracing for slower growth, if not uncertainty, in 2019, even though advanced packaging remains a bright spot in the market.
Generally, IC packaging houses saw strong demand in the first part of 2018, but the market cooled in the second half of the year due to a slowdown in memory. Going forward, the slower IC packaging market is expected to extend into the first part of 2019, although business may pick up by the second half. This, of course, depends on OEM demand, chip growth and geopolitical factors.
The trade tensions between the United States and China already have caused some packaging houses to slow their investments in China. But those trade issues are fluid. It’s still unclear what impact the proposed tariffs from China and the U.S. will have on the semiconductor industry.
This isn’t all doom and gloom. Advanced packaging continues to pick up steam, particularly approaches such as 2.5D, 3D, fan-out and system-in-package (SIP). In addition, new packaging technologies like chiplets and panel-level fan-out are emerging.
Overall, advanced packaging is playing a bigger role in the semiconductor market. Today, fewer device makers can afford to scale and migrate to advanced nodes like 10nm/7nm and beyond due to soaring IC design costs. Another way to get many of the benefits of scaling is by moving to heterogeneous integration, which puts multiple chips in an advanced package.
All told, advanced packaging is growing faster than the overall packaging market, but’s it not enough to offset a projected slowdown in the business. In the overall IC packaging market, “we expect a slowdown in 2019,” said Santosh Kumar, principal analyst at Yole Développement. “That’s throughout 2019.”
In 2019, the IC packaging market, which includes all technologies, is projected to reach $68 billion in terms of revenues, up 3.5% over 2018, according to Yole. In comparison, the IC packaging market is forecast to grow 5.9% in 2018, according to Yole. Meanwhile, “advanced packaging is projected to grow at 4.3% in 2019, compared to 2.8% for traditional/commodity packaging,” according to Kumar.
Unit growth for IC packaging is also a mixed bag. “The outlook for the packaging market in calendar 2019 is positive with an expected 5% to 10% increase in unit growth, albeit at a slightly slower pace compared to the last two years,” said Pieter Vandewalle, general manager of the ICOS division at KLA-Tencor.
Fig. 1: Advanced packaging revenue forecast by platform. (Source: Yole)
Packaging landscape
Generally, three types of entities develop chip packages—integrated device manufacturers (IDMs), foundries, and outsourced semiconductor assembly and test (OSAT) vendors.
Many IDMs develop packages for their own IC products. Then, some foundries, such as Intel, Samsung and TSMC, offer chip packaging services to customers. Most foundries, however, don’t develop IC packages. Instead, they hand off the packaging requirements to OSATs.
The OSATs are merchant vendors. At last count, there are more than 100 different OSATs in the market. A few OSATs are large, but most are small- to mid-sized players.
The OSAT industry has stabilized after years of consolidation. The last big merger occurred in 2018, when Advanced Semiconductor Engineering (ASE), the world’s largest OSAT, acquired Siliconware Precision Industries (SPIL), the fourth largest OSAT.
Nevertheless, packaging is a tough business. Customers want the OSATs to cut their packaging prices by 2% to 5% every year. Yet OSATs must maintain their R&D and capital spending budgets to stay ahead of the technology curve.
Packaging houses also must contend with the topsy-turvy business cycles. Typically the growth rates in packaging reflect the state of the semiconductor market.
Amid a slowdown in memory, the semiconductor market is projected to reach $490 billion in 2019, up 2.6% over 2018, according to the World Semiconductor Trade Statistics (WSTS) group. That compares to 15.9% growth in 2018, according to the WSTS.
Based on various forecasts, the leading-edge foundry business is poised for growth in 2019, but the memory outlook is mixed. “Even though memory prices have declined as compared to the same quarter last year, there is still growth,” said Doug Anberg, vice president of advanced lithography applications at Veeco. “Although the three largest global memory IDMs had some CapEx adjustments, they will continue to launch new technologies and new products, but at a slower ramp than initially planned.”
Meanwhile, the packaging market is changing. For years the smartphone was the key driver for packaging. Now there are numerous markets that will fuel the growth.
“AI will continue to be a major volume driver. Expect significant AI investments to continue,” Anberg said. “In the server/cloud industry, big data demands will require more processing power and higher bandwidth memory as the industry moves toward the 5G platform, driving silicon interposer and fan-out on substrate solutions.”
There are other market drivers. “We expect that the packaging market will continue to be focused on a wide variety of sectors beyond the mobile market, including automotive electronics, 5G, AI and machine learning,” KLA-Tencor’s Vandewalle said. “For the automotive segment, packaging quality requirements continue to increase; therefore, we expect equipment investments to upgrade automotive packaging lines.”
Some technologies are still emerging. “AI is one of the big drivers. IoT is another driver. Those are pieces that will drive business and business opportunities forward at a pretty fast pace,” said Terry Brewer, president and chief executive of Brewer Science. “We’re going to have self-driving and self-correcting cars. Those are coming, but we’re not there yet.”
Then, some markets, which were big drivers for packaging, are falling by the wayside, namely cryptocurrency.
Still to be seen, meanwhile, is how the trade issues between China and the U.S. will impact the market. “One of the topics that seems to be on everyone’s mind is the impact of tariffs and the trade tensions between the United States and China,” said Joanne Itow, managing director of manufacturing at Semico Research. “Partnerships, purchasing and inventory levels are all impacted by increased levels of uncertainty, and we already are seeing companies develop contingency planning scenarios.”
Wirebond, flip-chip markets
Over the years, meanwhile, the industry has developed a plethora of package types. One way to segment the packaging market is by interconnect type, which includes the following technologies—wirebond, flip-chip, wafer-level packaging and through-silicon vias (TSVs).
Today, some 75% to 80% of all IC packages use an older interconnect scheme called wire bonding, according to TechSearch. From a wafer start perspective, though, wire-bond packaging is growing at a rate of only 2.7% from 2016 to 2021, according to Prismark.
Developed in the 1950s, a wire bonder resembles a hi-tech sewing machine that stitches one chip to another chip or substrate using tiny wires. Wire bonding is used for low-cost legacy packages, mid-range packages and memory die stacking.
At the end of 2017, the utilization rates for wirebonding at the packaging houses were running at capacity. In comparison, due to the IC slowdown, wirebond utilization rates dipped to the 70% to 80% range or lower in the fourth quarter of 2018.
The sluggish business conditions are expected to extend into the first part of 2019. But by mid-2019 or sooner, business may pick up.
“We assume the trade tensions won’t get worse. So, if the trade tensions won’t get worse, we expect the March quarter to stabilize,” said Fusen Chen, president and chief executive at Kulicke & Soffa, in a recent conference call. “Hopefully, the delayed investments can turn into a ramp. In the second half of the fiscal year, we expect a ramp. Maybe it will start beyond the March quarter.”
Meanwhile, some changes are taking place in the wire-bond segment. In some products, DRAM dies are stacked in a package and connected using wire-bonding techniques. Now, DRAM vendors are migrating from wire-bond to flip-chip packaging as a means to boost I/O density.
This, in turn, will fuel the growth for advanced packaging in memory. “High-end memory solutions are moving to advanced packaging. Adoption of stacked DRAM with TSVs began in 2015 for high-bandwidth memory (HBM) and DIMMs,” Veeco’s Anberg said. “Mobile DRAM is converting to flip-chip packaging. The flip-chip business for memory packaging is expected to increase to 13% of the total market in 2022, generating new opportunities for copper pillar, chip-scale packaging, TSV and fan-out packaging.”
Fan-out, 2.5D and chiplets
Compared to wire-bond and flip-chip, fan-out is growing at a faster pace. Based on wafer starts, fan-out is projected to grow at a rate of 24.6% from 2016 to 2021, according to Prismark.
From a revenue perspective, the fan-out market is expected to grow 20% between 2018 and 2023, reaching $2.3 billion by 2023, according to Yole. “Fan-out packaging remains a healthy growing market with an annual growth of 19% from 2018 to 2019 in terms of revenue,” said Favier Shoo, an analyst with Yole.
Fan-out and a related technology, fan-in, fall in a category called wafer-level packaging (WLP). In WLP, the dies are packaged while on a wafer.
Neither fan-in or fan-out requires an interposer like 2.5D/3D, but the two WLP types are different. One distinction is how the two package types incorporate the redistribution layers (RDLs). RDLs are the copper metal connection lines or traces that electrically connect one part of the package to another. RDLs are measured by line and space, which refer to the width and pitch of a metal trace.
In fan-in, the RDL traces are routed inwards. In fan-out, the RDLs are routed inward and outward, enabling thinner packages with more I/Os.
Fan-out is driven by smartphones and other products. TSMC’s InFO technology, the most notable example of fan-out, is being used in Apple’s latest iPhones.
“Although many analysts are forecasting mobile device growth to be flat in 2019, the WLP content will continue to grow due to increasing processing power requirements coupled with ever-growing memory requirements,” Veeco’s Anberg said.
Others agree. “Mobile continues to be one main growth driver for both low-density and high-density fan-out,” said John Hunt, senior director of engineering for ASE. “Automotive will start to pick up momentum, as we get fan-out qualified for grade 1 and 2. And server applications are seeing growth for the high-end market.”
Generally, fan-out is segmented into two broad categories—standard density and high density. High-density fan-out has more than 500 I/Os with less than 8μm line/space. Amkor, ASE and TSMC sell high-density fan-out, which are geared for smartphones and servers.
Standard-density fan-out is defined as a package with less than 500 I/Os and greater than 8μm line/space.
The original fan-out technology—embedded wafer-level ball-grid array (eWLB)—is classified as a standard fan-out package type. Today, Amkor, ASE and JCET/STATS sell eWLB packages.
Competition is heating up here. ASE and Deca are ramping up the M-Series, a standard-density fan-out line that competes with eWLB. “The M-Series performs so much better reliability-wise than eWLB and wafer-level chip-scale packaging,” ASE’s Hunt said. “Some of our M-Series is fan-out. Some of it is fan-in. It’s a replacement for wafer-level CSP, because it has six-sided protection. So, it performs dramatically better.”
Fig. 2 M-Series vs. eWLB. (Source: ASE)
Traditionally, standard-density fan-out has been used in mobile and consumer applications. Now, fan-out is moving into automotive, which has been dominated by commodity packaging.
Fan-out is moving in some but not all segments. “I don’t see it in LiDAR, but I see radar. For automotive, it’s mainly infotainment. I see a move towards grade 0. Under the hood, that’s going to take some time. But eWLB grade 1, which is already out, is qualified. It’s not just one die but two die,” said Jacinta Aman Lim, deputy director at JCET/STATS ChipPAC.
Other types of fan-out are emerging. After years of R&D, panel-level fan-out packaging is beginning to ramp up in the market. “Samsung has already started HVM for panel fan-out. PTI and Nepes are currently in low-volume manufacturing and will start HVM next year with various products. By the end of 2019, ASE/Deca will probably start HVM of panel FO. Overall, we see higher adoption and more business of panel FO in 2019, compared to 2018,” Yole’s Kumar said.
Today’s fan-out technologies involve packaging a die in a round wafer format in 200mm or 300mm wafer sizes. In panel-level fan-out, the package is processed on a large square panel. This increases the number of die per substrate, which reduces manufacturing costs.
Fig. 3: Comparison of number of die exposed on 300mm wafer to number of die on panel. (Source: STATS ChipPAC, Rudolph)
Panel-level packaging has some challenges. “We believe (traditional) fan-out will be adopted more widely, especially for applications like mobile, where form factor is critical,” KLA-Tencor’s Vandewalle said. “Panel fan-out packaging technology will be further adopted, although not overnight. Substantial engineering work is needed to enable high-yield production. And standardization in terms of panel size and handling is required.”
Meanwhile, for years, the industry has been shipping 2.5D technology. In 2.5D, dies are stacked on top of an interposer, which incorporates through-silicon vias (TSVs). The interposer acts as the bridge between the chips and a board.
“2.5D enables an order of magnitude increase in interconnect density. What you are trying to address is memory bandwidth and latency. That’s the purpose of the interposer with very fine line and space,” said David McCann, vice president of packaging R&D and operations at GlobalFoundries.
2.5D/3D technologies, though, are relatively expensive, limiting the market to high-end applications like networking and servers.
Chiplets, meanwhile, are also emerging. With chiplets, you build systems like LEGOs. The idea is that you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme.
Government agencies, industry groups and individual companies are beginning to rally around various chiplet models.
So, momentum is building for chiplets. “This will accelerate innovation because you are designing only one part. This has been the driver among IP houses and the IP business in general. You grab one IP from here and another from there. But where this has run into problems is putting these IPs together. That part is tough,” said Amin Shokrollahi, chief executive of Kandou Bus.
Chiplets will take some time before it becomes mainstream. “There are several issues to overcome, such as standards, cost, testing and the supply chain,” according to Yole’s Kumar.
Chiplets, 2.5D, fan-out and other technologies are among the ways to put multiple dies in a package. As before, the industry hopes to use many of these schemes as an alternative to traditional chip scaling.
In packaging, the feature sizes are on a much larger scale, but you can still scale a device by reducing certain parts of the package, such as the bump pitch and RDLs.
For this and other apps, multi-die packaging or heterogeneous integration is catching on. “We expect adoption of advanced packaging solutions to continue for both logic and memory devices,” said Manish Ranjan, managing director at Lam Research. “The use of heterogeneous integration as a key enabler should also accelerate as companies adopt advanced packaging solutions to meet their future product requirements.”
To be sure, advanced packaging is moving in several directions and it gives customers new options. But there may be too many options on the table. The question is which packaging types will stick and which ones will become niches. Over time, some will likely fall by the wayside.
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