Scaling Bump Pitches In Advanced Packaging

Interconnects for advanced packaging are at a crossroads as an assortment of new package types are pushing further into the mainstream, with some vendors opting to extend the traditional bump approaches while others roll out new ones to replace them.

The goal in all cases is to ensure signal integrity between components in IC packages as the volume of data being processed increases. But as devices continue to shrink and more components are added into advanced packages to process, move, and store more data, new technologies with more I/Os will be required. So while traditional solder balls and/or copper microbumps still will be used for the foreseeable future, new technologies are under development that can augment or replace those interconnect technologies, increasing the number of I/Os and providing more headroom for scaling.

As always, size and cost are the determining factors. Copper microbumps are smaller than solder balls/bumps, enabling more I/Os in packages. In today’s advanced packages, the most advanced microbumps involve a 40μm pitch, which equates to 20μm to 25μm bump sizes with 15μm spacing between the adjacent bumps on the die.

Fig. 1: 2.5D/3D system architecture with HBM3 memory. Copper microbumps connect interposers and base dies. Microbumps are also used for the die-to-die connections. Source: Rambus

Beyond 40μm pitches, packaging customers have some options. First, they could develop packages using existing bumps technologies, which extend from 40μm pitches today down to 10μm, where these schemes run out of steam. Another option is a newer technology called copper hybrid bonding. In hybrid bonding, the dies are not connected using bumps in the package. Instead, they utilize tiny copper-to-copper interconnects, enabling finer-pitch packages with more I/Os than traditional packages. For packaging, the starting point for hybrid bonding is 10μm pitches and beyond.

AMD already is embracing copper hybrid bonding for future processor products. The company is using TSMC’s hybrid bonding technology. Other foundries also are working on hybrid bonding. But not all packages require hybrid bonding, and the technology is aimed at high-end products. Even then, hybrid bonding is an expensive and difficult process.

Instead of moving to hybrid bonding, Intel and others are looking to extend existing bump interconnect technologies and develop packages around them with pitches beyond 40μm. “It may still be advantageous to extend solder microbump interconnect to smaller pitches, utilizing the existing infrastructure while remaining compatible with existing silicon and packaging technologies,” said Zhaozhi Li, a packaging development engineer at Intel, at the recent ECTC conference.

Intel described a way to scale or reduce the bump pitch down to 10μm. Several OSATs also are working on finer-pitch copper bump technologies, as well. But as you scale solder/copper bump technology, the challenges increase. New materials, processes, and tools are required.

Nonetheless, both next-generation bump technology and hybrid bonding will play a vital role in the industry. They will propel the development of more advanced packages, as well as the chiplet model. For chiplets, a chipmaker may have a menu of modular dies in a library. Customers then can mix-and-match the chiplets and integrate them in an existing package type or new architectures.

Chiplets are emerging as an alternative to advance a chip design. Traditionally, to advance a design, vendors would develop a system-on-a-chip (SoC) and integrate more functions on the device at each generation. But this is becoming more difficult and expensive at each turn. While this method remains an option for new designs, chiplets promise to be the next big thing. Hybrid bonding or scaled bumps are among the critical pieces in the chiplet puzzle.

Packaging landscape
IC packages incorporate dies in an enclosure-like unit, which protects the devices from being damaged. Packages also can boost the performance of the dies.

“The industry is investing more on advanced packaging and has been diligently working to improve system-level interconnection density, reduce the power consumption, achieve a smaller form factor, and lower cost by scaling the package-level pitch and integrating more functions into a single package,” said Xiao Liu, senior program manager at Brewer Science.

The industry has developed more than 1,000 different packages. Customers select a package based on a given application.

One way to segment the packaging market is by interconnect type, such as wirebond, flip-chip, wafer-level packaging (WLP) and through-silicon vias (TSVs). TSVs provide the most I/Os, followed by WLP, flip-chip and wirebond.

Some 75% to 80% of packages are based on wire bonding, according to TechSearch. A wire bonder stitches one chip to another chip or substrate using tiny wires. Wirebonders are used to make commodity and mid-range packages as well as memory stacks.

With flip-chip, tiny solder or copper bumps are formed on top of a chip. The device is then flipped and mounted on a separate die or board. The bumps land on copper pads, forming an electrical connection.

In this process, the bump dies are connected using a high-speed flip-chip bonder, followed by a mass reflow process. “A lot of flip-chip devices don’t require fine pitches. They can be done with mass reflow,” said Bob Chylak, CTO of Kulicke & Soffa (K&S). “The flip-chip bonder takes the chip, dips the solder balls into a flux, and places them on the PCB. Then the PCB goes through a reflow oven, and the reflow oven melts the solder and then solidifies it.”

Flip-chip is used to develop many package types, such as ball grid array (BGA). Graphic chips and processors incorporate BGA packages. In flip-chip, the bump pitches on a chip range from 300μm to 50μm.

“We’re still seeing coarse-pitch packages at 140μm to 150μm. That’s still mainstream, and it’s not going to change anytime soon,” said Annette Teng, CTO of Promex, the parent company of QP Technologies. “We are starting to see some 110μm to 120μm. Below 40μm is still at the R&D level.”

Meanwhile, a fan-out package is one type of wafer-level package. In one example of fan-out, a DRAM die is stacked on a logic chip.

TSVs are used in advanced 2.5D/3D packages, which are generally for high-end systems. In 2.5D/3D, dies are stacked or placed side-by-side on top of an interposer, which incorporates TSVs. The TSVs provide an electrical connection from the dies to the board. In one example of 2.5D, an ASIC and high-bandwidth memory (HBM) are placed side-by-side on the interposer. (An HBM is a DRAM memory stack.)

With 2.5D, solder balls reside on the bottom of the substrate, electrically connecting the package to the board. C4 bumps, which are smaller structures, connect the substrate to the interposer. Smaller copper microbumps connect the interposer to the base dies. And in HBM, the DRAM dies are connected using tiny microbumps at 40μm pitches.

To stack and connect dies in these packages, a thermocompression bonding (TCB) system picks up a die and aligns the bumps to those from another die. The system bonds the bumps using force and heat.

Going forward, vendors want to develop HBM modules and 3D packages with bumps below 40μm pitches, enabling more I/Os and bandwidth. Chip customers could develop advanced packaging using finer bumps or go with copper hybrid bonding. Some may use both approaches for different packages.

Copper bumps are expected to extend from 40μm to 10μm pitches. Then, the industry needs to migrate to hybrid bonding, which enables interconnects with 10μm pitches and below. But not all packaging houses can develop hybrid bonding. It’s cost-prohibitive for most OSATs. It requires an expensive semiconductor fab to enable these processes.

Select foundries are among the only vendors capable of bringing hybrid bonding into production. Even then, hybrid bonding for packaging is challenging. “The big challenges for hybrid bonding are wafer surface cleanliness, wafer warpage, and step height between the copper and dielectric materials in a die,” said Tony Lin, technology director at UMC.

There are other issues, as well. “There will certainly be products introduced in the next couple of years with very fine pitches (using hybrid bonding),” said Mike Kelly, vice president of advanced packaging development and integration at Amkor. “This is an expensive process and will likely remain the venue of ultra-high performance for the next few years.”

Scaling the bumps
With that in mind, Intel and others are developing new advanced packages using traditional microbumps beyond 40μm. Vendors also are working on HBM3, a next-generation HBM technology with a 2X bump density over HBM2e. HBM3 enables 8.4Gbps of bandwidth, compared with 3.6Gbps for HBM2e.

Extending microbumps has some advantages. First, it leverages the existing solder/copper bump infrastructure. Second, several vendors are working on fine-pitch bump technologies, such as Amkor, ASE, Intel, JCET, Samsung and TSMC.

Developing packages with bumps isn’t new. In the 1960s, flip-chip packaging emerged as an assembly technology. Initially, flip-chip processes involved the formation of C4 (controlled-collapse chip connection) bumps, which range from 200μm to 75μm in diameter.

C4 bumps still are used in packages, but they are course-pitch structures. So starting at the 65nm node in 2006, Intel and others migrated to a smaller version of C4 bumps called copper microbumps/pillars, sometimes called C2 bumps. The initial copper microbumps were 25μm in diameter.

Copper bumps consist of a copper pillar with a thin nickel diffusion barrier and a tin-silver solder cap. “C2 bumps provide better thermal and electrical performances than C4 bumps. This is because the thermal conductivity and electrical resistivity of Cu are superior to those of solder,” said John Lau, CTO of Unimicron, in his new book entitled, “Semiconductor Advanced Packaging” (Springer, 2021).

To make the smaller copper microbumps, the process resembles the C4 flow. First, chips are processed on wafers in a fab. Bumps are then formed on the bottom of the wafer.

For this, the surface is deposited with an under-bump metallurgy (UBM) using deposition. Then, a light-sensitive material called a photoresist is applied on the UBM. Pre-determined bump sizes are patterned on top of the resist using a lithography system. That pattern is etched, forming a small gap.

Using an electrochemical deposition (ECD) system, the gap is filled or plated with a copper. The resist is stripped and the structure is etched. The structure is reflowed or heated in an oven, forming the bump.

Fig. 2: Microbump process flow. Source: John Lau, Unimicron

Today’s most advanced microbumps use a 40μm pitch and bump size between 20μm and 25μm. Bump sizes are about 50% of the bump pitch, according to DuPont.

Future packages will move to smaller copper bumps with finer pitches. “On pillar bumps, we have seen 18μm pitch with 9μm diameter and 20μm tall. There are about 200 million bumps on a 300mm wafer for 18μm pitch,” said Woo Young Han, product marketing manager at Onto Innovation. “We have heard a customer claim to have 10μm pitch with 5μm diameter and 10μm tall. There are about 500 million bumps on a 300mm wafer for 10μm pitch. 5μm bump diameter is the smallest we are hearing from our customers.”

Moving to smaller bumps presents some challenges. “As solder bump pitch scales down, the bump height becomes shorter, the bump surface available for bonding is reduced, and die-level bump count increases,” Han said. “The reduction in bump sizes with increased bump count translates into less margin for error to establish reliable electrical connections. Die-level bump co-planarity, bump surface roughness, and bump hardness become ever more critical as bump pitch scales down. Temperature, time and pressure used during bonding depend on the quality of die-level bump co-planarity, bump surface roughness, and bump hardness. Higher temperature, longer time, and more pressure used during bonding increase the cost and the risk of damaging the die.”

All of this presents several challenges throughout the manufacturing flow. Take etch, for example. “The diameter of the copper column and the solder bump is smaller. Under-cutting due to etching is becoming more critical,” Unimicron’s Lau said.

The ECD plating process is also challenging. “Plating uniformity and co-planarity control become increasingly important as customers target next-generation microbump solutions,” said Manish Ranjan, managing director at Lam Research. “Lam’s plating cell design delivers ultra-high uniform convection to enable fast deposition rates with uniformity. In addition, proprietary technology solutions, such as advanced surface treatment capability, enables lowest defectivity performance.”

On top of that, the shift towards smaller bumps also may require new and different bump structures. Consider a microbump with a 40μm pitch with a bump height of 25μm. In this bump, the height of the copper structure is 15μm, while nickel is 5μm. The remaining portion is the solder cap.

“In that structure, copper is larger than the nickel,” said Shashi Gupta, global marketing leader for advanced packaging technologies at DuPont. “As you go to finer pitches, the copper height will start shrinking. At some point, the thickness of the copper and the thickness of the nickel is more or less the same. The solder cap is shrinking, as well.”

In one hypothetical example, a future copper pillar might have a 3μm copper structure, a 3μm nickel barrier and a 5μm solder cap. “The point is that your nickel and copper are very similar now. At that thickness, it’s challenging to keep the uniformity that you’re looking to maintain across the wafer,” Gupta said. “So, you may need to consider picking one metal in your pillar structure with the solder on top.”

In other words, you might have a tiny copper pillar with a solder cap, or a nickel pillar with a solder cap in finer-pitch packages. “Instead of a copper/nickel/tin-silver structure, a copper/tin-silver or nickel/tin-silver structure is often used for cost, throughput or performance considerations,” Gupta said. “That will help the cost structure and it’s also easier to control the quality.”

Copper is a better metal, but there are some tradeoffs. Nickel has less conductivity, but nickel bumps also may work. This is still in R&D, and it’s unclear what will get implemented in production.

Nonetheless, in a future process, a copper bump would require only a copper plating process, while a nickel bump would utilize nickel plating.

This, in turn, simplifies the plating process. “Instead of plating two layers — a copper and then a nickel layer — it’s easier to plate a single layer of either copper or nickel. Then you put the same solder on top of it in a decreased volume amount,” Gupta said.

Eventually, two dissimilar bump metals are bonded together, and they diffuse into each other’s grain boundaries. That’s called an intermetallic compound (IMC) layer. In some cases, the IMC is strong. In other cases, the IMC is weak, causing the joint to fail.

The IMC is where problems could occur. “For a copper/tin-silver bump structure where solder is deposited directly on the copper pillar without the nickel barrier layer, an intermetallic compound (IMC) layer may form during reflow,” Gupta said. “The IMC layer may continue to grow through the aging or heating process to negatively impact the solder joint reliability and conductivity. In contrast, uniform nickel-plating replacing copper pillar is effective in restricting extensive IMC growth and offers excellent barrier capabilities, solderability, and other characteristics that are essential for consistent wafer fabrication. Newer nickel-based plating options are also sustainable from a process perspective.”

Fig. 3: Common pillar design and advance micropillar designs. Source: DuPont

Bump bonding
Making tiny bumps is challenging. Bonding them is also difficult at finer pitches.

Traditional flip-chip bonding with mass reflow is challenging at finer pitches. “Standard reflow processes are conducted in an oven for flip-chip and systems-in-package. It’s done in large quantities. It’s a cheaper solution,” said Nokibul Islam, senior director of field application engineering at JCET. “The concern is a global coefficient of thermal expansion mismatch between the substrate and chips could surface, resulting in higher warpage and die shifting.”

Traditional flip-chip processes work until 50μm or 40μm pitches, but then reliability issues may come into play. That’s where TCB fits in. Introduced several years ago, TCB is used for advanced fine-pitch bonding applications. Several vendors sell TCB tools.

TCB tools are used to bond dies with tiny bumps at 50μm to 40μm pitches and beyond, both for chip-to-wafer and chip-to-substrate applications. As it stands today, TCB extends down to 10μm pitches.

“Thermocompression bonding is local reflux,” K&S’ Chylak said. “Instead of heating the entire circuit board and all the chips on it, the thermal compression bonder grabs the die, dips it in flux just like a regular flip-chip, and places it on the PCB. There’s a heater in the bond head. That heats up past the melting point of solder holding the chip in place. Then it cools down so that the solder solidifies.”

Flux is used to get rid of the oxide that’s on the copper pad that you’re trying to bond. It dissolves the oxide in a chemical reaction.

TCB, however, is a relatively slow process with some flux cleaning issues. “There is a problem with both flip-chip and thermal compression bonding. The flux that you dip the bumps in to has to be cleaned,” Chylak said.

The industry uses cleaning systems to get rid of the flux in the package. That works for coarse-pitch applications, but this process takes time to clean the flux for fine-pitch packages.

In another possible solution, the industry has developed “no-clean flux” materials. Those materials don’t always work. If flux appears in the process, it’s hard to clean.

So K&S is developing a flux-less TCB technology. In a TCB tool, K&S incorporates an in-situ formic acid vapor delivery system and chamber. “We can put a vapor of formic acid, which will clean the surface without flux, and then we do the bond. This is a new technology that we’ve developed that can bond without flux. It’s a productivity and reliability improvement to TCB,” Chylak said.

There are other solutions. At ECTC, Siliconware, part of ASE, described a way to develop 3D packages with 20µm bump pitches. The goal was to stack and bond two thin dies. There were two test vehicles. One used TCB with a capillary underfill (TCCUF). The other used TCB with a non-conductive paste (TCNCP).

“In summary, we have successfully characterized and developed 3D packages using a 20µm bump pitch. This package can be achieved with standard die attached and reflow, as well as thermal compression bonding using NCF,” said Mu Hsuan Chan, a technical manager from Siliconware.

Intel, meanwhile, found a way to extend microbumps at 20μm and 10μm pitches. Intel developed dies with tiny bumps and bonded them using TCB tools with an alignment accuracy better than 2.1μm.

“The data suggest that a Cu/SnAg microbump configuration may be feasible at 20μm pitch with capable TCB tools and tight bonding process controls. However, at 10μm, a certain solder/Cu diffusion barrier metal needs to be implemented in order to preserve solder for the needs of TCB bonding as well as achieving enough bonding process margin,” Intel’s Li said.

Conclusion
Eventually, Intel and others will embrace hybrid bonding. TSMC plans to get an early jump on the technology.

But bumps will be around for a long time for both fine- and coarse-pitch packages. Nonetheless, both advanced bumps and hybrid bonding will enable fine-pitch interconnects for new advanced packages. It’s good to have more than one option on the table.

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