Once viewed as a low-cost IC packaging option, fan-out is going mainstream and upstream.
Chipmakers, OSATs and R&D organizations are developing the next wave of fan-out packages for a range of applications, but sorting out the new options and finding the right solution is proving to be a challenge.
Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and smartphones. In just one example of fan-out, a DRAM die is stacked on a logic chip in a package. This, in turn, brings the memory and processing functions closer together, providing more bandwidth in systems.
Fan-out isn’t the only advanced package type in the market, but it does have some advantages over competitive technologies like 2.5D and others.
“As part of advanced packaging, fan-out solutions have become critical and effective for increasing device performance and bandwidth,” said Stefan Chitoraga, an analyst at Yole Développement. In total, the fan-out packaging market is expected to grow from $1.475 billion in 2020 to $1.953 billion in 2021, according to Yole.
Fig. 1: Different options for high-performance compute packaging, interposer-based 2.5D vs. Fan-Out Chip on Substrate (FOCoS). Source: ASE
Fan-out packaging isn’t new. In fact, it’s been around since the mid-2000s. But the technology was under the radar until 2016, when Apple adopted TSMC’s fan-out package in the iPhone 7 and subsequent phones. Suddenly, other packaging houses developed a multitude of new and different fan-out packages. And today, the list of fan-out types continues to grow, making it difficult to keep track of the options and where they all fit.
Each version of fan-out comes with its own set of tradeoffs. Fan-outs can be developed using different manufacturing flows. They also can be made on round wafers or panels.
Their adoption is growing, too. Fan-out packages competed in a well-defined space in the past. Today, fan-out packaging is expanding in both the mid-range and high-end markets, where it may compete against other forms of advanced packaging.
Semiconductor Engineering examined the latest fan-out technologies in various applications, such as computing, mobile and networking, and where these solutions fit.
Packaging types
For years, packaging has been an important part of the semiconductor ecosystem. After a chipmaker processes a wafer in a fab, the dies on the wafer are diced and integrated in a package. A package encapsulates the chip, preventing it from being damaged. It also provides electrical connections from the device to the board.
There are many types of packaging, each geared for a specific application. One way to segment the packaging market is by interconnect type, which includes wirebond, flip-chip, wafer-level packaging (WLP) and through-silicon vias (TSVs). Interconnects are used to connect one die to another one. TSVs have the highest I/O counts, followed by WLP, flip-chip and wirebond.
Some 75% to 80% of today’s packages are based on wire bonding, which is an older technology, according to TechSearch International. A wire bonder stitches one chip to another chip or substrate using tiny wires. Wire bonding is used for low-cost legacy packages, mid-range packages and memory die stacking.
Quad-flat no-leads (QFN) and quad flat-pack (QFP) are two examples of wirebond-based packages. “We see stronger-than-ever demand for QFN packages,” said Rosie Medina, vice president of sales and marketing at QP Technologies. “They are used in many end markets, such as medical, commercial, and mil/aero. Handhelds, wearables, and boards with many components are prime applications.”
Flip-chip is another interconnect technology used for a number of package types, such as ball-grid array (BGA). In flip-chip, a sea of tiny copper bumps is formed on top of a chip. The device is then flipped and mounted on a separate die or board. The bumps land on copper pads, forming an electrical connection.
WLP is a technology that packages the dies while in a wafer-like format. Fan-out is considered a WLP technology.
2.5D/3D packages are used in high-end systems. In 2.5D/3D, dies are stacked or placed side-by-side on top of an interposer, which incorporates TSVs. In one example, an FPGA and high bandwidth memory (HBM) are placed side-by-side in a 2.5D package. An HBM is a DRAM memory stack.
“Through-silicon via (TSV) is the enabling technology of 3D-ICs as it provides electrical connections between the stacked chips. The main advantage of the 3D-IC technology with TSVs is that it provides a much shorter interconnection between different components, which results in lower resistive-capacitive delay and smaller device footprint,” said Luke Hu, a researcher at UMC, in a paper at the recent IEEE Electronic Components and Technology Conference (ECTC). Others contributed to the work on the paper, which described a pre-bond qualification process for TSVs.
2.5D/3D, fan-out and related technologies are considered advanced package types, which are designed to address several problems. For example, in systems, data moves back and forth between a separate processor and the memory devices on a board. But at times this exchange causes latency and increases energy consumption. One way to solve the problem is to bring the memory and processor closer and integrate them in an advanced package.
There are other applications, as well. Traditionally, to advance a design, chipmakers develop an ASIC. Then, at each node, they integrate more functions on the ASIC. But this methodology is becoming more expensive at each node.
Another way to get the benefits of scaling is by assembling complex and different dies in new forms of advanced packaging, sometimes called heterogeneous integration.
Fan-out flows
Fan-out, meanwhile, emerged in the mid-2000s. At the time, Infineon developed one of the first fan-out technologies. That technology, called embedded wafer-level ball-grid array (eWLB), was used to house Infineon’s baseband chip for cellular phones.
Later, Infineon licensed eWLB technology to three OSATs — ASE, Namium and STATS. (In 2015, JCET acquired STATS, while Amkor bought Nanium in 2017.)
Over time, packaging houses developed different types of fan-out beyond eWLB. In all cases, fan-out is different than other forms of advanced packaging, namely 2.5D/3D. Fan-out doesn’t require an expensive interposer, making it cheaper than 2.5D/3D.
Fan-out is also different than conventional packaging, where chips on a wafer are diced and then assembled in a package in one form or another.
In contrast, fan-out is a WLP type, meaning the dies are packaged in a wafer-like format. Fan-in packages, sometimes called chip-scale packages (CSP), are also a WLP type. “This type of packaging can create a wafer package that is nearly the same size as the original die,” said Sandy Wen, a process integration engineer at Coventor, a Lam Research Company. As a result, WLP-based packages are often used to save board space in systems.
Both fan-in and fan-out follow the same basic manufacturing flow. First, chips are processed on a wafer in a fab. Then, the chips on a wafer are diced. The dies are placed in a wafer based on an epoxy molded compound. This is called a reconstituted wafer.
Then, redistribution layers (RDLs) are formed on the mold compound in the polymer layers. RDLs are the copper metal connection traces that electrically connect one part of the package to another. RDLs are measured by line and space, which refer to the width and pitch of a metal trace.
Once these processes are completed, the individual packages on the reconstituted wafer are diced.
Fig. 2: Cross-section of the bottom of an RDL substrate. Source: Amkor
Fan-in and fan-out are different, however. In fan-in, the RDL traces are routed inward. As a result, fan-in is limited and runs out of steam at about 200 I/Os.
In fan-out, the RDL traces can be routed inward and outward, enabling thinner packages with more I/Os. “In fan-out, you expand the available area of the package,” said John Hunt, senior director of engineering at ASE. “Generally, I/Os refer to the connections that take the signals and/or power and ground connections either into the package or out of the package.”
Over the years, fan-out has moved toward RDLs with finer lines and spaces. “With the increase in system complexity, and the heterogeneous integration of large, high I/O dies into a package, the number of redistribution traces that are required to interconnect them is growing exponentially. In order to physically fit all of these interconnection traces within the package, we need to make the lines and spaces smaller,” Hunt said.
Five years ago, fan-out packages consisted of RDLs with 12μm line and 12μm space (12μm/12μm). “10μm/10μm is common now,” said Mike Kelly, vice president of advanced packaging development and integration at Amkor. “Today, the mainstream is 2μm/2μm with evolution to 1.5μm/1.5μm now and in 2022. 1.5μm/1.5μm will address 90% of the high-density fan-out products for the next three to four years. The leading-edge will be 1μm/1μm starting maybe next year for a few select products.”
Not all fan-out is alike. Today, there are three manufacturing flows for fan-out —chip-first/face-down, chip-first/face-up, and chip-last.
eWLB and other types are made using the chip-first/face-down approach. “In this approach, singulated die are placed die pad side down into a thermal release adhesive on a temporary carrier. The dies are overmolded on the carrier. The resulting reconstituted plastic wafer with dies are de-bonded from the carrier, and the RDLs are connected directly to the die pads,” ASE’s Hunt said.
Chip-first die-up is different. “The incoming wafer first has copper pillars plated on the die pads. The dies are then singulated and placed die facing up into the thermal release adhesive on a temporary carrier. The dies are overmolded on the carrier. The resulting reconstituted plastic wafer with dies are de-bonded from the carrier. The RDLs are now connected to the surface of the exposed copper pillars,” Hunt said.
Chip-last is another option. First, the RDLs are formed on a temporary carrier. “The dies are flip-chip attached to the RDL on the carrier and overmolded. The carrier is then released, and final backend processing is completed,” Hunt said.
There are some challenges. During the process, the reconstituted wafer is prone to warpage. Then, when the dies are embedded in the compound, they tend to move, causing an unwanted effect called die shift. This impacts the yields.
There are some solutions, at least for warpage. At ECTC, Brewer Science presented a paper on a single-layer mechanical debonding adhesive. “The material presented in this work can provide several advantages over other material systems, such as 1) ultrathin wafer handling; 2) high-thermal stability; 3) low warpage for high-stress substrates; 4) single coating and baking to reduce cost of ownership and improve throughput, and 5) simple material cleaning,” said Xiao Liu, senior program manager at Brewer Science. Others contributed to the work.
Mobile fan-out
Going forward, vendors continue to develop fan-out, which is split into two segments—standard density and high density. Geared for mobile and IoT, standard-density fan-out is defined as a package with less than 500 I/Os and greater than 8μm line/space. Geared for high-end systems, high-density fan-out has more than 500 I/Os and less than 8μm line/space.
It’s not that simple, though. Each vendor may have several options for both standard- and high-density fan-out. And each option may have different configurations, package sizes and integration schemes.
It may take a scorecard to decipher the options. One way to get a handle on the market is by looking at some of the main applications for fan-out, namely smartphones, computing and networking. Fan-out also has been spotted in automotive and IoT.
Smartphones represent one application. For some time, Apple has incorporated fan-out in the iPhone, which is used to package one critical device—the application processor. Phones also consist of a multitude of other chips, all of which require a mix of package types.
Not all smartphones incorporate advanced packages, particularly for the application processor. Today, many phones incorporate traditional flip-chip BGA packages for the processor. These packages are less expensive and more mature.
Nonetheless, Amkor, ASE, JCET and TSMC are separately developing fan-out packages for the latest smartphones. In the latest example, TSMC introduced a new fan-out technology for mobile called InFO_B. This package resembles its current InFO package, where a DRAM die is stacked on a logic part. In InFO_B, TSMC develops the bottom part (logic) of the package. But in a major change, the DRAM stacking or attaching process is conducted by a third party, such as an OSAT, rather than by TSMC.
This allows customers the flexibility to incorporate DRAM dies from different vendors in the package. “It offers better electrical performance than the flip-chip solutions,” said Jerry Tzou, director of advanced packaging business development at TSMC, in a presentation.
Fan-out also is being developed for the infrastructure in 5G. Today, carriers are deploying 5G networks at sub-6GHz frequencies. Some carriers are deploying next-generation 5G networks using the mmWave frequency bands at 26GHz, 28GHz and 39GHz.
The industry is developing new IC packages for 5G mmWave. These packages combine an RF chip and the antenna in the same unit, which is called antenna-in-package (AiP). The idea behind these new integrated antenna schemes is to bring the RF chips closer to the antenna to boost the signal and minimize the losses in systems.
At ECTC, Fraunhofer IZM, Technical University Berlin, and GlobalFoundries described a project that involves the development of mmWave 5G modules for small cell base stations. This project involves the development of a chip-last double-molded fan-out package with AiP.
The package integrates two modules. The bottom module consists of analog front-end IC, based on GlobalFoundries’ 22nm FD-SOI technology. The top module integrates two antennas.
“The targeted package size is 10 x 10mm², and the integrated antenna array consists of a 2 x 2 patch antenna array with dual-band operation at 28GHz and 39GHz, with a minimum required impedance bandwidth of 400MHz in both bands,” said Tanja Braun, group manager at Fraunhofer IZM, in a paper at ECTC.
2.5D vs. fan-out
Meanwhile, several vendors are developing fan-out for the high-end computing and networking markets. In some cases, high-end systems incorporate different chips on a board, such as processors, memory, and others. But placing discrete chips on a board takes up too much space and is inefficient in moving data from one device to another.
That’s where 2.5D fits in. By putting multiple chips in a 2.5D package, OEMs can achieve more functionality in a smaller form-factor. It brings the chips closer together, enabling more memory bandwidth.
2.5D also is designed to handle larger chip architectures. In some cases, the chip architectures consist of multiple dies, which won’t fit on a single interposer. It may require two or more interposers to accommodate all dies.
To develop larger interposers, chipmakers pattern several interposers on a wafer using a lithography scanner. The scanner can print features in a field size of 26mm x 33mm. That field size denotes what many call the reticle limit.
So an interposer at reticle size is roughly 26mm x 33mm. Meanwhile, in the fab, a vendor may take two separate interposers and stich them together, creating a bigger interposer that can accommodate more dies in a 2.5D package.
All told, 2.5D is fast and provides more I/Os, but it is also expensive. So the industry is looking for lower-cost alternatives. “We are going to see more large-area fan-out for high-performance applications as an alternative to silicon interposers,” said Jan Vardaman, president of TechSearch International.
Amkor, ASE, TSMC and others are separately working on large-area, high-density fan-out, which supports several logic dies and HBMs. All of these come at standard package sizes.
Fan-out also is going beyond the 1X reticle size. At ECTC, for example, TSMC presented a paper on a 2.5X reticle size of fan-out (2100mm2) with a 110 x 110mm2 substrate. It has 5 layers of RDLs at 2μm/2μm.
This package is ideal for networking equipment. Typically, networking vendors develop a large ASIC to handle the switching functions in these systems. But the ASIC is becoming larger and more costly at each generation. So some vendors are breaking up the large ASIC into smaller dies and integrating them into a package. A multi-chip module (MCM) is one option. MCMs, which integrate dies in a module, can have RDLs at 15μm/15μm.
Fan-out is another option. In one configuration within a networking system, TSMC’s fan-out package can incorporate two logic dies and eight I/O dies. The logic dies are in the middle of the package with two I/O dies on each of the four sides.
Using finer pitch RDLs with more I/Os, TSMC’s new fan-out package outperforms the MCM by 7X, according to a paper presented at ECTC by Y.P. Chiang, a TSMC researcher.
Others also are developing large-area fan-out. The trick is to connect multiple dies in the package without using an interposer.
For some time, ASE has been developing a fan-out technology called Fan Out Chip on Substrate (FOCoS), including both chip-first and chip-last versions.
At ECTC, ASE described a new technology called sFOCoS, which is a fan-out package featuring a silicon bridge. Basically, a bridge consists of a tiny piece of silicon with routing layers, which connects one chip to another inside a package.
This isn’t a new concept. Intel has developed a silicon bridge for packaging. Now, Amkor, ASE and TSMC are developing similar technologies.
“The advantage of a silicon bridge technology is to provide better scalability and design flexibility to allow high-density die-to-die interconnections with line spacing smaller than 1μm X 1μm,” said Lihong Cao, director of engineering and technical marketing at ASE, in a presentation.
In one configuration, an ASIC and HBM are stacked side-by-side in a fan-out package. ASE’s bridge is embedded in the package, and connects the ASIC to the HBM. The bridge die size is 6mm x 6mm with a bump pitch at 55μm.
Meanwhile, Amkor described a bridge/connect technology, dubbed S-Connect. “S-Connect technology has been developed using a multi-chip, fan-out interposer with various functionalities, such as a die-to-die connection, where integrated passive devices and active devices can be integrated,” said JiHun Lee, an R&D engineer at Amkor, at ECTC.
Amkor’s solution comes in two configurations. The first option resembles a small fine-pitch silicon interposer. The second option uses a multilayer RDL, which is fabricated in a mold compound.
More fan-out
Other types of fan-out are in the works, too. For example, A*STAR described a fan-out package for deep neural networks. The package incorporates four dies, based on 22nm FD-SOI. The dies are connected using Intel’s Advanced Interface Bus (AIB), a die-to-die PHY-level standard.
Then, at ECTC, JCET and Wingcomm described a hermetic eWLB technology for fiber-optic communication (FOC) apps. Two FOC devices have been incorporated in the package, including a 25Gb/s optical receiver/transmitter and a 100Gb/s quad-channel transmitter.
Conclusion
Clearly, fan-out is an enabling technology. It gives customers new packaging options.
Even more options are expected over time as the popularity of this packaging approach grows. But sorting these out and integrating them is not simple, even for the most sophisticated design teams.
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