Companies seek economies of scale in advanced packaging, but that isn’t straightforward.
Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging.
Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes.
Fan-out packaging on a large square panel is significantly more difficult, and mass adoption is not expected anytime soon. Still, one of the problems with all advanced packaging is the cost, and companies such as ASE, Powertech, Nepes, and Samsung are looking to panel-level packaging to provide economies of scale. A panel processes more packages than a round wafer, which reduces the cost. For example, a 300mm wafer can process 2,500 6mm x 6mm packages, but a 600mm x 600mm panel can accommodate 12,000 packages, according to ASE.
Figure 1. Fan-out packaging with (a) wafer form and (b) panel form. Source: ASE
Figure 2. Package outline of PLFO device with (a) top view and (b) cross-section view. Source: ASE.
Still, after years in the works, panel-level fan-out remains challenging. To date, Powertech and Samsung are the only vendors in limited production. Most are still developing or exploring the technology, while others have dismissed it.
Standards are among the stumbling blocks here. Several companies are developing the technology using different panel sizes. This makes it difficult for some equipment makers to invest and make systems for the technology. In addition, panel fan-out requires large volumes to keep the lines running. There are few, if any, high-volume products that could fill up an entire panel-level line today.
“You can’t do a panel unless you have a high-volume runner,” said Jan Vardaman, president of TechSearch International, at the recent International Wafer-Level Packaging Conference (IWLPC). “You absolutely need something that’s in high-volume or you can’t do it, because you can’t fill the lines.”
Generally, with the traditional wafer format, fan-out packaging vendors in total have enough capacity to meet demand for now. For this and other reasons, the mass adoption of panel fan-out is being pushed out. At one time, mass production was slated for 2019. “It’s maybe at the end of next year, but it’s not this year,” Vardaman said. “It’s probably more like the 2021 or 2022 time frame.”
Nonetheless, there is a great deal of activity in the arena. Among the key developments:
Panel challenges
Traditionally, IC vendors relied on chip scaling to advance their devices. In scaling, the idea is to pack more transistors on a monolithic die at each process node, enabling faster chips with a lower cost per transistor.
Chip scaling isn’t going away, but it’s becoming more difficult and expensive at each node, prompting many IC vendors to look for alternatives. Another way to get the benefits of scaling is by putting multiple different chips in an advanced package, also known as heterogeneous integration.
Advanced packaging has been around for years. But today there are a number of new advanced packaging options on the table. Companies that currently offer packages or parts of the solution are evaluating new and different options.
“Advanced packaging will become more important in the post-Moore’s Law era,” said Steven Liu, vice president of corporate marketing at UMC. “UMC and others play a critical role in the 2.5D interposer market, which was adopted and in mass production by leading global customers. Although UMC doesn’t provide a fan-out packaging solution, we will continue to investigate other new advanced packaging approaches or collaborate with OSAT partners.”
At the high-end of the packaging market, the industry uses 2.5D technologies. In 2.5D, dies are stacked or placed side-by-side on top of an interposer, which incorporates through-silicon vias (TSVs). The interposer acts as the bridge between the chips and a board.
Meanwhile, in fan-out packaging, the dies are packaged on a wafer, usually referred to as wafer-level packaging (WLP). In just one example of fan-out, a DRAM die is stacked on top of a logic chip in a package.
“You don’t have to limit it to a single die with fan-out,” said John Hunt, senior director of engineering at ASE. “You can do both heterogenous and homogeneous integration, where you split your dies up and combine them in a fan-out package. You use the advantages of electrical connectivity in fan-out to interconnect different dies.”
Amkor, ASE, JCET, TSMC and others sell fan-out packages based on the traditional wafer-level format. Apple, Infineon, NXP, Qualcomm and others are using fan-out packages.
Fan-out is ideal for automotive, servers, smartphones and other systems. “Fan-out is beginning to pick up steam in general,” said Shankar Muthukrishnan, senior director of lithography marketing at Veeco. “More and more OSATs and IDMs are beginning to go into volume manufacturing, and we expect the trend to continue.”
Not all chips require fan-out. In fact, a large percentage of today’s chips are housed in more conventional and cheaper package types.
Cost is one of the big hurdles with fan-out. To get broader adoption of fan-out, the industry continues to drive down the cost of the technology. Another way to reduce the cost is to move toward a panel-level production process.
Panel-level processing is challenging, however. Vendors are developing the technology using various panel sizes, such as 510mm x 415mm, 510mm x 515mm, 600mm x 600mm, and others.
The lack of standards is problematic for the equipment industry. Some equipment vendors have developed tools for some but not all panel sizes. Still others are waiting on the sidelines until a standard size emerges and the market takes off.
In response, SEMI is hammering out a panel-size standard. The trade group has narrowed the panel options to two sizes—510mm x 515mm and 600mm x 600mm.
Regardless, the industry needs a standard. “We have to agree on a uniform panel size,” said Joseph Dang, an applications engineer at AT&S during a panel discussion at IWLPC. “It affects the equipment that we manufacture these substrates on. It affects electroless copper plating and lithography tools. All of these require specific equipment to handle specific panel sizes. They are not flexible to handle various sizes. It causes a chaotic environment, where we have six, seven or eight substrate suppliers with different panel sizes.”
Economics also plays a role. It costs about $100 million to $200 million to build a panel-level production line. Yet a company must have enough volume to ensure a return. Otherwise, it’s a money-losing proposition.
It doesn’t make sense to run small lots on a panel. For high-volume devices, though, panels make more sense. “Still, there are a lot of challenges. Where are the high volumes for this kind of technology?” asked Choon Heung Lee, CTO at JCET.
The first panel fan-out packages in production involve low-density products, not high-end packages. It’s hard to get a decent return on lower-margin products.
And if that’s not enough, panel fan-out has many of the same manufacturing challenges as wafer-level fan-out. Generally, in the wafer fan-out flow, a wafer is processed in a fab. The chips on the wafer are diced and placed in a wafer-like structure, which is filled with an epoxy mold compound. This is called a reconstituted wafer.
Then, the redistribution layers (RDLs) are formed within the compound. RDLs are the copper metal connection lines or traces that electrically connect one part of the package to another. RDLs are measured by line and space, which refer to the width and pitch of a metal trace.
In wafer fan-out packages, the mainstream RDL technology is 5-5µm line/space and above, but some are developing leading-edge packages at 1-1µm and below.
Fan-out isn’t a simple process. During the flow, the wafer-like structure is prone to warpage. Then, when the dies are embedded in the wafer, they tend to move, causing an unwanted effect called die shift. This impacts the yield.
Generally, panel fan-out follows a similar manufacturing flow. The difference, of course, is that dies are processed in a panel. But as with wafer fan-out, a panel is also prone to warpage. Die shift is an issue with some RDLs challenges.
Still, the industry has proven it can make panel fan-out packages with less aggressive RDLs, which are 5μm-5μm and above. This involves packages that house simpler ASICs and power management ICs (PMICs).
Eventually, the industry wants to produce panel fan-out packages at 2μm-2μm and below. This involves high-density packages with complex ASICs, processors and memory cubes.
“We are talking about trying to incorporate at least two or three times more dies in the actual package. 2μm-2μm will give you more in a smaller space,” said Keith Best, director of applications engineering at Onto Innovation. Onto was recently formed after the merger of Nanometrics and Rudolph.
Making panel fan-out at 2μm-2μm is easier said than done. “First, standardization of a panel size has yet to surface,” said Kim Yess, technology director for WLP materials at Brewer Science. “For panels, getting below 2µm line/space becomes very challenging due to the warp of the substrate, and also the capabilities of the tooling and materials chosen for patterning. I’m not sure that ≤2µm interconnects make true sense for panel processes, as they are able to create a larger number of devices than the market/customers are demanding. Additionally, this process in the beginning will not be as cost-effective as using standard 300mm equipment and processes.”
In the panel process flow, there are several critical steps with various equipment. For example, lithography is the key technology that patterns the RDLs and other parts of the package. In wafer-level fan-out, these tools are capable of patterning the RDLs at 2µm-2µm and below.
Lithography tools also are available for panel fan-out, but the challenges are different. “Keep in mind that the larger the panel, there will be more of an impact on yield and also warpage, which can impact the productivity and cost,” Veeco’s Muthukrishnan said. “The movement of die in panel fan-out will impact the resolutions that can be achieved. Achieving 2-2µm resolution will be challenging and may cost more than expected. It’s possible for panel to achieve this in the future, but may involve additional steps or increased process costs.”
Besides lithography, panel fan-out requires other types of equipment. “We have seen significant progress on the adoption of panel fan-out packaging over the last year with more players starting pilot production and some already having high-volume manufacturing,” said Pieter Vandewalle, general manager of KLA’s ICOS division. “While 2-2µm and below is already running on R&D samples, we believe it will take several years to see this in high-volume manufacturing on panel. Most processing tools are available. However, the main challenge seems to be in achieving high yield numbers.”
Inspection and metrology are also a critical part of the flow. Inspection tools look for defects on wafers or packages, while metrology systems characterize the structures.
“2-2µm inspection and metrology are already available for wafer-level processing,” Vandewalle said. “Panel-level 2D and 3D inspection and metrology tools are available for low-volume manufacturing and will play a critical role in progressing the adoption of panel fan-out.”
Panel may require different inspection/metrology techniques. For example, CyberOptics sells a metrology unit based on phase shift profilometry technology. It identifies and rejects multiple reflections caused by shiny components and mirror-like surfaces.
“Whether we are inspecting a wafer or panel doesn’t change anything from our perspective,” said Subodh Kulkarni, president and CEO of CyberOptics. “Panel inspection customers seem to prefer the technology with larger fields of views to cover the entire panel faster.”
Who is doing what?
Today, roughly a half-dozen companies are working on panel fan-out, while others have different strategies. Intel, for example, has been developing panel-level processes for packaging, but not for fan-out. TSMC, meanwhile, has no plans to develop panel fan-out technology, saying that wafer fan-out meets all requirements.
Others are pursuing it. Last year, for example, SEMCO rolled out the industry’s first panel fan-out package. Incorporated in Samsung’s Galaxy smartwatch, the package combines an application processor with a PMIC. It features three layers of RDL at 7μm-8μm.
After recently acquiring SEMCO’s panel unit, Samsung is moving forward with the technology. “We are planning the next product for wearable devices. The basic mission is to implement more functions within the limited form factor,” said Junghwa Kim from Samsung in a paper at IWLPC.
To reduce the package size in panel fan-out, Samsung is exploring the idea of stacking two dies on top of each other, according to the paper.
Meanwhile, for some time, ASE has been developing panel fan-out using a 600mm x 600mm format. In panel, ASE is looking to move into production within the next year. “We will use panel for both low-density products and high-density 2μm and less line and space products,” ASE’s Hunt said. “It’s for networking applications and the new AI. AI requires more computing power and memory.”
Today, ASE is shipping wafer-level fan-out packages based on its own technology. It also produces the M-Series wafer fan-out line based on the technology from a company called Deca. Deca has developed a technology that calculates and compensates for die shift during the production flow.
For panel fan-out, ASE plans to put Deca’s M-Series into production, as well as a proprietary high-density fan-out package called Fan Out Chip on Substrate (FoCoS).
ASE is developing a version of the FoCoS fan-out technology with high-bandwidth memory (HBM). Targeted for high-end systems, HBM stacks DRAM dies on top of each other and connects them through the stack with TSVs, enabling more I/Os and bandwidth.
Typically, HBM is integrated in a more expensive 2.5D package. “The problem is the cost is relatively high. The sourcing for interposers is challenging,” Hunt said.
FoCoS doesn’t require an interposer, making it less expensive than 2.5D. The largest FoCoS package can incorporate about 9 dies, resulting in a relatively large package. “We can put 10 to 12 packages on a 300mm wafer, which is not economically practical for production,” he said.
Instead, ASE wants to use panel for these large package types to reduce the cost. “We want to use the 600mm panel because those packages can get rather large,” he added.
Meanwhile, Nepes has been developing a proprietary panel fan-out technology using a 600mm x 600mm format.
On top of that, Nepes recently acquired Deca’s wafer-level packaging manufacturing line in the Philippines. Nepes also has licensed Deca’s technology.
Eventually, Nepes will produce wafer- and panel-level packages based on Deca’s technology. So the industry now has two sources for Deca’s technology—ASE and Nepes.
Powertech, meanwhile, is shipping panel fan-out, at least in limited production. Then, a group that includes ASM Pacific, Dow, Huawei, Indium, JCAP and Unimicron are developing it.
And not to be outdone, a European project, called smart-MEMPHIS, is developing piezo-MEMS harvesting devices using panel fan-out. The device incorporates a MEMS-based energy harvester, an ASIC and a supercapacitor. Applications include pacemakers and wireless sensor networks for health monitoring.
Panel fan-out is a key enabler here. “The technology is well suited for applications like the targeted energy harvester, where heterogeneous components have to be integrated into a miniaturized system,” said Tanja Braun, deputy group manager at Fraunhofer, which is part of the smart-MEMPHIS project.
Conclusion
Clearly, panel fan-out gives customers some new options. But it will take time before the technology takes off.
It will also require more investments. Some vendors with deeper pockets will make it happen. But the payback is uncertain. As a result, some may end up throwing in the towel over time.
Related Stories
 |
 |
 |
 |
 |
 |
 |  |
Leave a Reply