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IEEE P2416

Power Modeling Standard for Enabling System Level Analysis
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Description

Scope: This standard proposes a meta-model / meta-standard focused on parameterization and abstraction, enabling system, software and hardware IP-centric power analysis and optimization. This standard defines concepts for the development of parameterized, accurate, efficient and complete power models for systems and hardware IP blocks usable for system power analysis and optimization. These concepts include, but are not limited to, process, voltage and temperature (PVT) independence, power and thermal management interface, workload and architecture parameterization. Such models are suitable for use in software development flows and hardware design flows, as well as representing both pre-silicon estimated and post-silicon measured data. This standard also defines the necessary requirements for the information content of parameterized, accurate, efficient, and complete power models, to help guide development and usage of other related power, workload and functional modeling standards, such as UPF IEEE Std-P1801, SystemC IEEE Std- 1666, SystemVerilog IEEE Std-1800, and possibly others. Beyond defining the concepts and related standard requirements, the proposed specification recommends the use of other relevant design flow standards (e.g. IP-XACT) with the objective of enabling more complete and usable power-aware design flows.
Purpose: This standard supports the ability to develop accurate, efficient, and interoperable power models for complex designs, to be used with a variety of commercial products throughout an electronic system design, analysis, and verification flows.

Need for the Project: The increasing importance of power issues has spawned an interest in power-aware design flows. The problem of energy efficient system design cannot be solved in isolation, and needs to be addressed holistically. All use contexts–as seen from the point of view of software developers, system architects and reliability engineers–must be considered. Parameterized power models are a key piece of enabling such comprehensive, energy efficient systems.
These models should accurately reflect power dependence on workload and be usable for early power estimation. In particular, using existing modeling capabilities, it is very difficult to create accurate (good predictability of the amount and type of power consumed) and complete (all power events represented) power models for IP block designs which exhibit more than simple power behavior. Besides the needs of accuracy, completeness and conciseness, for any power model to be effective it must be transportable between applications that operate at different levels of abstraction (such as software programming, pre-design estimation, TLM simulation, RTL simulation, etc.), and it must address power variability issues by supporting PVT independence and power contributor segregation. Finally, the modeling techniques should be usable across different types of semiconductor IP. While some power modeling capabilities exist today, they are mainly geared for modeling low-level primitives, and are insufficient for modeling more complex objects that make up SoCs, and complete systems that may include software. These issues, among others, motivate the need for development of new standards for modeling IP blocks and entire systems; models with a sufficient level of accuracy and flexibility in order to be useful in a comprehensive power-aware design flow.

When proposing power modeling standards, related areas of use and design steps relevant to each domain must be considered. Isolated, power-aware standards exist, but none are designed to address power awareness comprehensively. Because of the inter-relationships between these different domains, and pre-existence of some standards in each, it is best to begin with a syntax-agnostic path, and focus on developing semantic aspects of these parameterized power models–models enabling comprehensive, energy efficient systems.


  • Other names: Power Modeling Standard for Enabling System Level Analysis
  • Type: EDA