Dynamic voltage and frequency scaling (DVFS) techniques—along with associated techniques such as dynamic voltage scaling (DVS) and adaptive voltage and frequency scaling (AVFS)—are very effective in reducing power, since lowering the voltage has a squared effect on active power consumption. DVFS techniques provide ways to reduce power consumption of chips on the fly by scaling down the voltage (and frequency) based on the targeted performance requirements of the application. Since DVFS optimizes both the frequency and the voltage, it is one of the only techniques that is highly effective on both dynamic and static power.
Dynamic voltage scaling is a subset of DVFS that dynamically scales down the voltage (only) based on the performance requirements. Adaptive voltage and frequency scaling is an extension of DVFS. In DVFS, the voltage levels of the targeted power domains are scaled in fixed discrete voltage steps. Frequency-based voltage tables typically determine the voltage levels. It is an open-loop system with large margins built in, and therefore the power reduction is not optimal. On the other hand, AVFS deploys closed-loop voltage scaling and is compensated for variations in temperature, process, and IR drop using dedicated circuitry (typically analog in nature) that constantly monitors performance and provides active feedback. Although the control is more complex, the payoff in terms of power reduction is higher.
In the implementation stage, DVFS is accomplished using a combination of MSV and multi-mode/multi-corner (MMMC) techniques. Utilizing power domains is a requirement for implementing DVFS designs. In addition, these power domain definitions must be consistent with front-end definitions of power domains.
DVFS differs from MSV in that with DVFS, a single power domain may operate at different modes, where each mode has a different supply voltage and operating frequency.
In implementation with DVFS, the challenges are very similar to DVFS in synthesis: juggling different operating voltages (with their assigned, different timing libraries) and different operating frequencies (different timing constraint files). In more advanced EDA tools, these different combinations are optimized in parallel, automating the process. Although this may result in longer run times to achieve design closure than with traditional, non-DVFS designs, the power benefits are worthwhile.
The example shows DVFS techniques implemented in the layout. In the baseline or active mode of operation, all blocks operate at 125MHz and 1.08V. In slow mode, one block operates at 66MHz and 0.9V, which conserves power. In standby, two of the blocks are powered down completely.
On a sample of designs, DVFS can improve dynamic power by 40-70% and provide 2X to 3X improvement in leakage. It can have up to 10% area impact and adds complexity due to the inclusion of level shifters, power-up sequence requirements and clock scheduling which can impact design turn-around time.
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