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Power Gating

Reducing power by turning off parts of a design
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Description

Power shut-off is the single most efficient way to reduce leakage power. If a block is not used, it is powered down, greatly reducing power.

Synthesis uses the power domain concept to describe switchable blocks (switchable power domain) and always-on portions of the design (always-on power domain). Isolation cells are needed to prevent the unwanted propagation of signals from power-down domain to power-on domains.

The main task during synthesis is the adding isolation cells. Otherwise, synthesis is not largely affected by PSO unless it needs to insert state retention cells and/or always-on cells. The connection of power switch cells to the power control module happens during the physical implementation flow, when physical information is known.

If the design has multiple power domains, a new set of DFT challenges will need to be addressed. For example, how to control and stabilize various power domains during test, how to create controllability and observability for the low-power structures (isolation cells, power shut-off gates, state retention registers, etc.), and how to minimize the power during the test application.

There are two types of PSO:
On-chip power shut-off means that power switches within the SoC control the power shut-off
Off-chip power shut-off means the power switches are external to the chip



PSO (or power gating) can also be either fine- or coarse-grained, referring to the size of each logic block controlled by a single power switch. With fine-grained power gating, power can be shut off to individual blocks or cells without shutting off the power to other blocks—which continue to operate. This can help to reduce active mode leakage power, or leakage during normal operation. With coarse-grained power gating, power is gated very coarsely, as with a single sleep signal that powers down the entire chip. This reduces leakage only during standby.

On a sample of designs, power shutoff can reduce leakage power by 10-50X. It has no impact on dynamic power. Timing will be impacted, adding between 4 and 8 percent due to the addition of isolation logic, complex timing and wakeup sequences and rush currents. The area penalty is likely to be between 5 and 15% due to isolation cells, state retention cells and always on logic. Larger power grid may be necessary due to power rush. Additional complexity is added to many stages of the design flow including verification, synthesis, DFT and implementation.

Page contents originally provided by Cadence Design Systems


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