A class library built on top of the C++ language used for modeling hardware
SystemC is a class library built on top of the C++ language. Work started on it in 1996. There is some contention about the origins of the language. One source cites its origins as being the Scenic language which was worked on between Synopsys and UC Irvine and later Siemens. Others say it came out of work in Motorola. Frontier and IMEC (commercialized in CoWare) also may have had significant contributions.
The class library, together with a set of macros, implements an event-driven simulator. The principle extensions beyond C++ are the ability to define concurrency, to add timing information and an extended set of datatypes. Version 1.0 of the standard, released Mar 28th 2000, mimicked the existing Hardware Description Languages (HDL) in that it provided a structural hierarchy, signal-level connectivity, clock-cycle accuracy, delta cycles necessary for dealing with zero delays, four-valued logic (0, 1, X, Z), and bus-resolution functions. A reference implementation was provided as the standard.
Version 2, released Feb 1st 2001, extended SystemC into a higher level of abstraction adding abstract communications, transaction-level modeling, and capabilities for the creation of virtual platforms (VP) modeling. This release added abstract ports, dynamic processes, and timed event notifications.
Given that is was possible to define multiple levels of abstraction with 2.0, two sets of recommended abstractions were defined called Loosely Timed (LT) and Approximately Timed (AP). LT models had minimal timing defined. These would be fast executing models aimed at virtual prototypes developed for software execution. AP models had a lot more timing information included and would be better suited for performance analysis, architectural exploration and form the basis of a hardware development flow.
It is possible to combine the two timing models together, but this would produce a slower overall model without having the additional capabilities.
There are several subgroups working on standards related to SystemC:
SystemC Configuration, Control and Inspection (CCI) WG. This working group is responsible for developing standards that allow tools to interact with models in order to perform activities such as setup, debug and analysis.
No standards have yet been released.
SystemC Analog Mixed Signal (AMS) WG. This working group standardizes abstract AMS and RF modeling extensions for SystemC.
SystemC AMS 1.0 released in 2010
2.0 released in 2014
IEEE 1666.1 expected in 2015
There has been little adoption of this standard even though a number of organizations within Europe are using it.
SystemC Language WG
Also has a Transaction Level Modeling (TLM) sub-group.
This working group is responsible for the definition and development of the SystemC and TLM core languages, the foundation on which all other SystemC libraries and functionality are built.
SystemC core language (SystemC 2.3.1) released April 25th 2014
SystemC Synthesis WG
Define the SystemC synthesis subset that can be used to synthesize digital hardware from high-level specifications.
No standard published yet.
SystemC Verification WG. Defines verification extensions to SystemC enabling deployment of modern verification methodologies with this language.
SystemC verification (SCV 2.0) released April 25th 2014
Modeling and Simulation of ARM Processor Architecture: Using SystemC
SystemC: From the Ground Up, Second Edition
Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems
- Other names: IEEE 1666
- Type: EDA