Knowledge Center

Knowledge Center

Pin Swapping

Lowering capacitive loads on logic
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Description

By swapping gate pins, switching occurs at gates/pins with lower capacitive loads.

In design with low-power intent, synthesis tools automatically perform a variety of power optimization techniques, including pin swapping.


The diagram shows an automated pin-swapping algorithm. The pins are swapped so that most frequently, switching occurs at the pins with lower capacitive load. Since the capacitive load of pin A is lower, there is less power dissipation.

On a sample of designs, pin swapping reduced dynamic power by less than 5%. It had no significant impact on any other aspects of the design flow.

Page contents originally provided by Cadence Design Systems


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