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Multi-Vt

Use of multi-threshold voltage devices
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Description

Multi-Vth optimization utilizes gates with different thresholds to optimize for power, timing, and area constraints. Most library vendors provide libraries that have cells with different switching thresholds. A good synthesis tool for low-power applications is able to mix available multi-threshold library cells to meet speed and area constraints with the lowest power dissipation. This complex task optimizes for multiple variables and so is automated in today’s synthesis tools.

The most common leakage reduction technique is to use specially designed high- Vth cells where possible in the netlist. The low- Vth gates switch more quickly in response to their input signals, but consume more leakage power. The high- Vth gates switch more slowly, but consume less leakage power.



The synthesis tool should be able to limit the maximum leakage power for the design by performing multi- Vth leakage optimization. The compiler chooses cells with high Vth to replace the cells with low Vth in areas where it won’t affect critical timing paths. Low- Vth cells are placed in areas that do not meet timing.

Current EDA technology has matured so that multi-Vth optimization is automated from RTL through GDS. Basic requirements are different threshold voltage libraries of the same cell’s functionality, and a power-aware implementation tool. High-Vth cells are low-power, but lower performance as well. Low-Vth cells consume more power, but provide higher performance. Usually the tradeoff favors power. For example, by using a high-Vth cell instead of low-Vth cell, the user can achieve a significant reduction (up to 80 percent) in leakage power with a small impact to timing (around 20 percent).

Different Vth versions of the same functional cell usually have the same footprint, so the cells can be swapped interchangeably and easily during layout. However, the timing impact of using different Vth cells has to be taken into account during cell swapping. The implementation tool also usually handles this analysis automatically.

Multiple threshold voltage swapping usually takes place either in the post–clocktree synthesis implementation stage or the post-route stage.

On a sample of designs, Multi-Vth optimization reduced leakage power by a factor of 2-3X with an area variation of plus or minus 2% It had no significant impact on any other aspects of the design flow.

Page contents originally provided by Cadence Design Systems


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