Power consumption is dependent on both the physical structures on the chip and the mode of operation. With today’s multi-mode SoCs, determining the correct stimulus to verify average and peak power across a variety of modes is increasingly challenging.
Generally, designers will want to obtain early estimates of power based on available stimulus. For more accurate power estimates, switching activity data is obtained by simulating test cases with real system stimulus. Often, such simulation is not available until later in the design cycle. Designers need to use the most accurate testbench available at any given point in the design flow and revise their estimate as new stimulus becomes available. If switching activity data is not available from simulation, designers should estimate the switching activity on the chip’s primary inputs and apply that estimate within the power analysis tool. Transient switching power can be estimated based on the number of flip-flops, combinatorial gates, and clock speed.
Annotate switching activity using accurate switching activity data when available. To get a more accurate estimate, run simulation of the final netlist to generate a switching activity file in one of the standard formats.
Simulation tools support the switching activity information needed for power optimization and power analysis. This information needs to be provided before running generic synthesis. Switching activity can be annotated into the compiler by loading a .vcd, .saif, or .tcf file.
The toggle count format (.tcf) file contains switching activity in the form of the toggle count information and the probability of the net or pin to be in the logic 1 state. Synthesis tools propagate the switching activities throughout the design.
The functional simulations are Verilog or VHDL simulations. The functional simulation is carried out to generate the toggle count format file (.tcf, .saif, or switching activity) by running the testbench on the RTL or synthesized gate-level netlist.
The .tcf generated by running simulation on the RTL is used as an input for accurate power analysis in synthesis.
Also, consider the simulation mode when generating switching activities. A zero-delay gate-level simulation will not account for any natural glitching that occurs in combinatorial logic, and will result in an optimistic power calculation.
If gate-level simulation is required for power analysis, use an SDF delay-based gate-level simulation.
Use libraries that represent the worst-case power. Synthesis is done using worstcase timing libraries to optimize for area, timing, and power concurrently, but they do not necessarily represent the worst-case power. Dynamic power is usually the highest in fast conditions, which can be represented by the best-case timing libraries.
Use accurate wire modeling. Every designer knows about the inaccuracies of wire load models when it comes to timing closure. Yet, many design teams use a “zero” wire load model for synthesis, resulting in inaccurate power estimation.
Use a reasonable wire load model or one of the “physical based” wire-modeling technologies available in today’s synthesis tools.
Physical layout estimation is a physical modeling technique that bypasses wire loads for RTL synthesis optimization. This may take the form of an equation to model the wire delay. Physical layout estimation uses actual design and physical library information and dynamically calculates wire delays for different logic structures in the design. In most cases, physical layout estimation–synthesized designs correlate better with place-and-route tools.
Page contents originally provided by Cadence Design Systems