As this design paradigm is getting more and more attention, commercial silicon is starting to employ it, particularly for applications where performance is less important than battery life or overall system power.
Rather than operate transistors in normal mode of operation at Vdd, the voltage is reduced to allow it to operate in the knee of the transistor curve.
There are a number of downsides to this approach. First and foremost, performance is reduced significantly, by a factor similar to or worse than power gains. Second, there is higher variability. Third, leakage is increased. There also can be functional failures, particularly with respect to memory.