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Power-Aware Test

Test considerations for low power circuitry
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Description

Typically, to achieve testability in a SoC device, various DFT structures are inserted in the design, such as memory BIST, boundary scan, and internal scan. Most of these DFT structures are inserted in the synthesized structural (gate-level) netlist.

If the design has multiple power domains, a new set of DFT challenges will need to be addressed. For example, how to control and stabilize various power domains during test, how to create controllability and observability for the lowpower structures (isolation cells, power shut-off gates, state retention registers, etc.), and how to minimize the power during the test application.

For low-power test, there are two key issues. First, the design must be testable. On-tester power consumption can dwarf operational power consumption, even at tester clock speeds, because efficient test patterns cause a very high percentage of the logic to be switching at a given time. Some chips would melt on the tester unless different blocks are shut down at different times, as they are in various functional modes of operation. So, for Power Shut-Off (PSO) test, scan chains must be constructed to minimize power domain crossing and to bypass switchable domains when they are shut down.

Once the design partitioning is understood, the second issue can be addressed. Power-aware manufacturing tests can be created. These tests now have two goals: limit the switching activity on the chip and test the advanced power logic such as level shifters, PSO logic, and state retention gates.

EDA solutions may combine DFT capabilities, such as constructing scan chains that are power domain aware, with advanced test pattern generation. To reduce power consumption during manufacturing test, these power domain–aware scan chains can be controlled during test by inserting logic that enables direct control of which power domains are being tested. Combined with power domain–aware ATPG, this solution tests advanced power structures and reduces power consumed during test.



Also, the vectors themselves can be constructed so that the changing values of the “filler” bits are controlled to reduce the switching activity. This means that the power consumed during the shifting of the scan patterns is controllable.

Page contents originally provided by Cadence Design Systems


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