Knowledge Center

Knowledge Center

Clock Gating

Dynamic power reduction by gating the clock


In most designs, data is loaded into registers very infrequently, but the clock signal continues to toggle at every clock cycle. Often, the clock signal drives a large capacitive load, making these signals a major source of dynamic power dissipation.

Clock gating reduces power dissipation for the following reasons:
• Power is not dissipated during the idle period when the register is shut-off by the gating function
• Power is saved in the gated-clock circuitry
• The logic on the enable circuitry in the original design is removed

Clock-Enabled Register Example

Consider a multiplexer (MUX) at the data input of a register. This MUX is controlled by an enable signal. The inferred logic block in the original RTL, before and after the clock-gating attribute is set is shown below.

Synthesis sees this type of description as a perfect candidate for clock gating. If the data input to a flip-flop can be reduced to a MUX between the data pin and the output pin of the flip-flop, the synthesis tool can model this flip-flop by connecting the “data input” directly to the data pin of the flip-flop, and by using the MUX enable to gate the clock signal of the flip-flop via an inserted clock-gating element as illustrated.

De-Cloning Local Clock Gating

If the clock-gating logic of different registers in the design uses the same enable signal, RTL Compiler can merge these clock-gating instances for any such identically gated registers. This process is called clock-gating de-cloning.

Page contents originally provided by Cadence Design Systems

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