Knowledge Center

Knowledge Center

Clock Tree Optimization

Design of clock trees for power reduction


Portions of the clock tree(s) that aren’t being used at any particular time are disabled.

In normal operation, the clock signal continues to toggle at every clock cycle, whether or not its registers are changing. Clock trees are a large source of dynamic power because they switch at the maximum rate and typically have larger capacitive loads.

If data is loaded into registers only infrequently, a significant amount of power is wasted. By shutting off blocks that are not required to be active, clock gating ensures power is not dissipated during the idle time.

Clock gating can occur at the leaf level (at the register) or higher up in the clock tree. When clock gating is done at the block level, the entire clock tree for the block can be disabled. The resulting reduction in clock network switching becomes extremely valuable in reducing dynamic power.

Today, clock gating to address dynamic power is done in almost all designs, not just low-power designs. The reason is that clock-gating technology in EDA tools has evolved to where it is automated and easy to implement, and doesn’t break the methodology.

Clock gating is first defined in the synthesis stage and optimized in the implementation stage.

In the synthesis stage, clock-gating elements are inserted; however, in the synthesis stage there usually is no exact information on the physical distance between the clock-gating element and the leaf cell. Clock-gating violations usually occur because the clock-gating cell is too far from the leaf cell. During physical implementation, to fix clock-gating violations, the clock-gating cell must be physically moved closer to the leaf cell. However, if the clock-gating cells are completely de-cloned, this isn’t possible until clock-gating cloning is done.

Conversely, overdoing clock-gating cloning will introduce many clock-gating elements, thereby nullifying the power and area advantage provided by clock gating.

In the physical realm, the implementation tool now knows exactly how far the clock-gating cell is from the leaf pin. This enables the tool to correctly clone the clock-gating element to prevent clock-gating timing violations.

Therefore, the correct methodology to deal with clock gating is to de-clone all the way during synthesis, and then selectively clone based on clock-gating timing during the physical implementation stage. This is a process that is automated by an EDA tool during the clock tree synthesis implementation stage.

For a sample of designs, clock gating provided 20% dynamic power savings with no impact on leakage power and very little impact on circuit timing. There is a slight area penalty that could be around 2%. It has very little impact on design and verification flows.

Page contents originally provided by Cadence Design Systems

Advertise Here
Advertise your products or services directly

Advertise Here
Advertise your products or services directly



We want to hear from you. If you have any comments or suggestions about this page, please send us your feedback.